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Commit 0e767189 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
Browse files

drm/i915: Add a brief description of the VLV display PHY internals 



Document the internal structure of the VLV display PHY a bit to help
people understand how the different register blocks relate to each
other.

v2: Add a bit more text
    Make it a DOC: comment, but leave the ascii art out since
    it would get mangled

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarChon Ming Lee <chon.ming.lee@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 46470fc9

Documentation/DocBook/drm.tmpl

+4 −0
Original line number Original line Diff line number Diff line
@@ -2937,6 +2937,10 @@ int num_ioctls;</synopsis> 
	  probing, so those sections fully apply.

	  probing, so those sections fully apply.

        </para>

        </para>

      </sect2>

      </sect2>

      <sect2>

        <title>DPIO</title>

!Pdrivers/gpu/drm/i915/i915_reg.h DPIO

      </sect2>

    </sect1>

    </sect1>





    <sect1>

    <sect1>

drivers/gpu/drm/i915/i915_reg.h

+81 −4
Original line number Original line Diff line number Diff line
@@ -575,12 +575,89 @@ enum punit_power_well { 
#define  DSI_PLL_M1_DIV_MASK			(0x1ff << 0)

#define  DSI_PLL_M1_DIV_MASK			(0x1ff << 0)

#define CCK_DISPLAY_CLOCK_CONTROL		0x6b

#define CCK_DISPLAY_CLOCK_CONTROL		0x6b





/*

/**

 * DPIO - a special bus for various display related registers to hide behind

 * DOC: DPIO

 *

 * VLV and CHV have slightly peculiar display PHYs for driving DP/HDMI

 * ports. DPIO is the name given to such a display PHY. These PHYs

 * don't follow the standard programming model using direct MMIO

 * registers, and instead their registers must be accessed trough IOSF

 * sideband. VLV has one such PHY for driving ports B and C, and CHV

 * adds another PHY for driving port D. Each PHY responds to specific

 * IOSF-SB port.

 *

 * Each display PHY is made up of one or two channels. Each channel

 * houses a common lane part which contains the PLL and other common

 * logic. CH0 common lane also contains the IOSF-SB logic for the

 * Common Register Interface (CRI) ie. the DPIO registers. CRI clock

 * must be running when any DPIO registers are accessed.

 *

 * In addition to having their own registers, the PHYs are also

 * controlled through some dedicated signals from the display

 * controller. These include PLL reference clock enable, PLL enable,

 * and CRI clock selection, for example.

 *

 * Eeach channel also has two splines (also called data lanes), and

 * each spline is made up of one Physical Access Coding Sub-Layer

 * (PCS) block and two TX lanes. So each channel has two PCS blocks

 * and four TX lanes. The TX lanes are used as DP lanes or TMDS

 * data/clock pairs depending on the output type.

 *

 * Additionally the PHY also contains an AUX lane with AUX blocks

 * for each channel. This is used for DP AUX communication, but

 * this fact isn't really relevant for the driver since AUX is

 * controlled from the display controller side. No DPIO registers

 * need to be accessed during AUX communication,

 *

 * Generally the common lane corresponds to the pipe and

 * the spline (PCS/TX) correponds to the port.

 *

 * For dual channel PHY (VLV/CHV):

 *

 *  pipe A == CMN/PLL/REF CH0

 *

 *

 * DPIO is VLV only.

 *  pipe B == CMN/PLL/REF CH1

 *

 *  port B == PCS/TX CH0

 *

 *  port C == PCS/TX CH1

 *

 * This is especially important when we cross the streams

 * ie. drive port B with pipe B, or port C with pipe A.

 *

 * For single channel PHY (CHV):

 *

 *  pipe C == CMN/PLL/REF CH0

 *

 *  port D == PCS/TX CH0

 *

 * Note: digital port B is DDI0, digital port C is DDI1,

 * digital port D is DDI2

 */

/*

 * Dual channel PHY (VLV/CHV)

 * ---------------------------------

 * |      CH0      |      CH1      |

 * |  CMN/PLL/REF  |  CMN/PLL/REF  |

 * |---------------|---------------| Display PHY

 * | PCS01 | PCS23 | PCS01 | PCS23 |

 * |-------|-------|-------|-------|

 * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3|

 * ---------------------------------

 * |     DDI0      |     DDI1      | DP/HDMI ports

 * ---------------------------------

 *

 *

 * Note: digital port B is DDI0, digital pot C is DDI1

 * Single channel PHY (CHV)

 * -----------------

 * |      CH0      |

 * |  CMN/PLL/REF  |

 * |---------------| Display PHY

 * | PCS01 | PCS23 |

 * |-------|-------|

 * |TX0|TX1|TX2|TX3|

 * -----------------

 * |     DDI2      | DP/HDMI port

 * -----------------

 */

 */

#define DPIO_DEVFN			0

#define DPIO_DEVFN			0