Commit 0e47b598 authored Mar 02, 2016 by Wolfram Sang Committed by Thierry Reding Mar 23, 2016

pwm: lpc18xx-sct: Test clock rate to avoid division by 0



The clk API may return 0 on clk_get_rate(), so we should check the
result before using it as a divisor.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>

parent bea307c1

drivers/pwm/pwm-lpc18xx-sct.c

+5 −0

Original line number	Diff line number	Diff line
		@@ -360,6 +360,11 @@ static int lpc18xx_pwm_probe(struct platform_device *pdev)
		}

		lpc18xx_pwm->clk_rate = clk_get_rate(lpc18xx_pwm->pwm_clk);
		if (!lpc18xx_pwm->clk_rate) {
		dev_err(&pdev->dev, "pwm clock has no frequency\n");
		ret = -EINVAL;
		goto disable_pwmclk;
		}

		mutex_init(&lpc18xx_pwm->res_lock);
		mutex_init(&lpc18xx_pwm->period_lock);