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Commit 0d017e21 authored by Florian Fainelli's avatar Florian Fainelli Committed by David S. Miller
Browse files

net: bcmgenet: update bcmgenet_ephy_power_up to clear CK25_DIS bit 



The CK25_DIS bit controls whether a 25Mhz clock is fed to the GPHY or
not, in preparation for powering down the integrated GPHY when relevant,
make sure we clear that bit.

Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent ca8cf341

drivers/net/ethernet/broadcom/genet/bcmgenet.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -354,6 +354,7 @@ struct bcmgenet_mib_counters { 
#define EXT_GPHY_CTRL			0x1C

#define EXT_GPHY_CTRL			0x1C

#define  EXT_CFG_IDDQ_BIAS		(1 << 0)

#define  EXT_CFG_IDDQ_BIAS		(1 << 0)

#define  EXT_CFG_PWR_DOWN		(1 << 1)

#define  EXT_CFG_PWR_DOWN		(1 << 1)

#define  EXT_CK25_DIS			(1 << 4)

#define  EXT_GPHY_RESET			(1 << 5)

#define  EXT_GPHY_RESET			(1 << 5)





/* DMA rings size */

/* DMA rings size */

drivers/net/ethernet/broadcom/genet/bcmmii.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -178,7 +178,7 @@ static void bcmgenet_ephy_power_up(struct net_device *dev) 
		return;

		return;





	reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL);

	reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL);

	reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN);

	reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN | EXT_CK25_DIS);

	reg |= EXT_GPHY_RESET;

	reg |= EXT_GPHY_RESET;

	bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);

	bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);

	mdelay(2);

	mdelay(2);