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Commit 0cc40dac authored by jerin jacob's avatar jerin jacob Committed by Ralf Baechle
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MIPS: CMP: Fix physical core number calculation logic 



The CPUNum Field in EBase register is 10bit wide, so after 1 bit right
shift, the mask value should be 0x1ff.

Signed-off-by: default avatarjerin jacob <jerinjacobk@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/4420/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent a1226540

arch/mips/kernel/smp-cmp.c

+1 −1
Original line number Diff line number Diff line
@@ -97,7 +97,7 @@ static void cmp_init_secondary(void) 


	/* Enable per-cpu interrupts: platform specific */



	c->core = (read_c0_ebase() >> 1) & 0xff;

	c->core = (read_c0_ebase() >> 1) & 0x1ff;

#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)

	c->vpe_id = (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) & TCBIND_CURVPE;

#endif