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Commit 0c241d5b authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Disable FIFO underrun reporting around IBX transcoder B workaround 



Doing the IBX transcoder B workaround causes underruns on
pipe/transcoder A. Just hide them by disabling underrun reporting for
pipe A around the workaround.

It might be possible to avoid the underruns by moving the workaround
to be applied only when enabling pipe A. But I was too lazy to try it
right now, and the current method has been proven to work, so didn't
want to change it too hastily.

Note that this can re-enable underrun reporting on pipe A if was
already disabled due to a previous actual underrun. But that's OK, we
may just get a second underrun report if another real underron occurrs
on pipe A.

v2: Note that pipe A underruns can get re-enabled due to this (Jani)

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> (v1)
Link: http://patchwork.freedesktop.org/patch/msgid/1446225802-11180-1-git-send-email-ville.syrjala@linux.intel.com
parent c465613b

drivers/gpu/drm/i915/intel_dp.c

+11 −0
Original line number Diff line number Diff line
@@ -3655,6 +3655,13 @@ intel_dp_link_down(struct intel_dp *intel_dp) 
	 * matching HDMI port to be enabled on transcoder A.

	 */

	if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) {

		/*

		 * We get CPU/PCH FIFO underruns on the other pipe when

		 * doing the workaround. Sweep them under the rug.

		 */

		intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);

		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);



		/* always enable with pattern 1 (as per spec) */

		DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);

		DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
@@ -3664,6 +3671,10 @@ intel_dp_link_down(struct intel_dp *intel_dp) 
		DP &= ~DP_PORT_EN;

		I915_WRITE(intel_dp->output_reg, DP);

		POSTING_READ(intel_dp->output_reg);



		intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A);

		intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);

		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);

	}



	msleep(intel_dp->panel_power_down_delay);

drivers/gpu/drm/i915/intel_drv.h

+9 −0
Original line number Diff line number Diff line
@@ -1079,6 +1079,15 @@ intel_wait_for_vblank(struct drm_device *dev, int pipe) 
{

	drm_wait_one_vblank(dev, pipe);

}

static inline void

intel_wait_for_vblank_if_active(struct drm_device *dev, int pipe)

{

	const struct intel_crtc *crtc =

		to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));



	if (crtc->active)

		intel_wait_for_vblank(dev, pipe);

}

int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);

void vlv_wait_port_ready(struct drm_i915_private *dev_priv,

			 struct intel_digital_port *dport,

drivers/gpu/drm/i915/intel_hdmi.c

+11 −0
Original line number Diff line number Diff line
@@ -1108,6 +1108,13 @@ static void intel_disable_hdmi(struct intel_encoder *encoder) 
	 * matching DP port to be enabled on transcoder A.

	 */

	if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B) {

		/*

		 * We get CPU/PCH FIFO underruns on the other pipe when

		 * doing the workaround. Sweep them under the rug.

		 */

		intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);

		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);



		temp &= ~SDVO_PIPE_B_SELECT;

		temp |= SDVO_ENABLE;

		/*
@@ -1122,6 +1129,10 @@ static void intel_disable_hdmi(struct intel_encoder *encoder) 
		temp &= ~SDVO_ENABLE;

		I915_WRITE(intel_hdmi->hdmi_reg, temp);

		POSTING_READ(intel_hdmi->hdmi_reg);



		intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A);

		intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);

		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);

	}



	intel_hdmi->set_infoframes(&encoder->base, false, NULL);

drivers/gpu/drm/i915/intel_sdvo.c

+11 −0
Original line number Diff line number Diff line
@@ -1464,12 +1464,23 @@ static void intel_disable_sdvo(struct intel_encoder *encoder) 
	 * matching DP port to be enabled on transcoder A.

	 */

	if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {

		/*

		 * We get CPU/PCH FIFO underruns on the other pipe when

		 * doing the workaround. Sweep them under the rug.

		 */

		intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);

		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);



		temp &= ~SDVO_PIPE_B_SELECT;

		temp |= SDVO_ENABLE;

		intel_sdvo_write_sdvox(intel_sdvo, temp);



		temp &= ~SDVO_ENABLE;

		intel_sdvo_write_sdvox(intel_sdvo, temp);



		intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A);

		intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);

		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);

	}

}