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Commit 0bd4b346 authored by Sebastian Hesselbarth's avatar Sebastian Hesselbarth
Browse files

ARM: dts: berlin: add scu and chipctrl device nodes for BG2/BG2Q 



This adds scu and general purpose registers device nodes required for
SMP on Berlin BG2 and BG2Q SoCs. The secondary CPUs will pick their jump
address from general purpose (SW generic) register 1.

Signed-off-by: default avatarSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: default avatarAlexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: default avatarAntoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: default avatarJisheng Zhang <jszhang@marvell.com>
Tested-by: default avatarAntoine Tenart <antoine.tenart@free-electrons.com>
parent 55d3de54

arch/arm/boot/dts/berlin2.dtsi

+10 −0
Original line number Diff line number Diff line
@@ -72,6 +72,11 @@ 
			cache-level = <2>;

		};



		scu: snoop-control-unit@ad0000 {

			compatible = "arm,cortex-a9-scu";

			reg = <0xad0000 0x58>;

		};



		gic: interrupt-controller@ad1000 {

			compatible = "arm,cortex-a9-gic";

			reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
@@ -176,6 +181,11 @@ 
			};

		};



		generic-regs@ea0184 {

			compatible = "marvell,berlin-generic-regs", "syscon";

			reg = <0xea0184 0x10>;

		};



		apb@fc0000 {

			compatible = "simple-bus";

			#address-cells = <1>;

arch/arm/boot/dts/berlin2q.dtsi

+10 −0
Original line number Diff line number Diff line
@@ -87,6 +87,11 @@ 
			cache-level = <2>;

		};



		scu: snoop-control-unit@ad0000 {

			compatible = "arm,cortex-a9-scu";

			reg = <0xad0000 0x58>;

		};



		local-timer@ad0600 {

			compatible = "arm,cortex-a9-twd-timer";

			reg = <0xad0600 0x20>;
@@ -183,6 +188,11 @@ 
			};

		};



		generic-regs@ea0110 {

			compatible = "marvell,berlin-generic-regs", "syscon";

			reg = <0xea0110 0x10>;

		};



		apb@fc0000 {

			compatible = "simple-bus";

			#address-cells = <1>;