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Commit 0bcf6aa7 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/net-next 



Jeff Kirsher says:

====================
This series contains updates to ixgbevf and e1000e.

Alex's ixgbevf patch is meant to address several race issues that become
possible because next_to_watch could possibly be set to a value that shows
that the descriptor is done when it is not.  In order to correct that we
instead make next_to_watch a pointer that is set to NULL during cleanup,
and set to the eop_desc after the descriptor rings have been written.

Stephen's ixgbevf patch makes the PCI id table a const and reformats the
table to match what the ixgbe driver does.

The remaining 13 patches from Bruce are cleanup patches for e1000e to
resolve checkpatch.pl warnings/errors, removing blank lines where
necessary and fix code formatting.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents c031e234 3ffcf2cb

drivers/net/ethernet/intel/e1000e/80003es2lan.c

+65 −66
Original line number Diff line number Diff line
@@ -37,7 +37,9 @@ 
 * "index + 5".

 */

static const u16 e1000_gg82563_cable_length_table[] = {

	 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };

	0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF

};



#define GG82563_CABLE_LENGTH_TABLE_SIZE \

		ARRAY_SIZE(e1000_gg82563_cable_length_table)
@@ -393,7 +395,7 @@ static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 
		 * before the device has completed the "Page Select" MDI

		 * transaction.  So we wait 200us after each MDI command...

		 */

		udelay(200);

		usleep_range(200, 400);



		/* ...and verify the command was successful. */

		ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
@@ -403,13 +405,13 @@ static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 
			return -E1000_ERR_PHY;

		}



		udelay(200);

		usleep_range(200, 400);



		ret_val = e1000e_read_phy_reg_mdic(hw,

						   MAX_PHY_REG_ADDRESS & offset,

						   data);



		udelay(200);

		usleep_range(200, 400);

	} else {

		ret_val = e1000e_read_phy_reg_mdic(hw,

						   MAX_PHY_REG_ADDRESS & offset,
@@ -462,7 +464,7 @@ static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 
		 * before the device has completed the "Page Select" MDI

		 * transaction.  So we wait 200us after each MDI command...

		 */

		udelay(200);

		usleep_range(200, 400);



		/* ...and verify the command was successful. */

		ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
@@ -472,17 +474,17 @@ static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 
			return -E1000_ERR_PHY;

		}



		udelay(200);

		usleep_range(200, 400);



		ret_val = e1000e_write_phy_reg_mdic(hw,

		                                  MAX_PHY_REG_ADDRESS & offset,

		                                  data);

						    MAX_PHY_REG_ADDRESS &

						    offset, data);



		udelay(200);

		usleep_range(200, 400);

	} else {

		ret_val = e1000e_write_phy_reg_mdic(hw,

		                                  MAX_PHY_REG_ADDRESS & offset,

		                                  data);

						    MAX_PHY_REG_ADDRESS &

						    offset, data);

	}



	e1000_release_phy_80003es2lan(hw);
@@ -666,9 +668,7 @@ static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, 
	s32 ret_val;



	if (hw->phy.media_type == e1000_media_type_copper) {

		ret_val = e1000e_get_speed_and_duplex_copper(hw,

								    speed,

								    duplex);

		ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);

		hw->phy.ops.cfg_on_link_up(hw);

	} else {

		ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw,
@@ -754,9 +754,9 @@ static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw) 


	/* Initialize identification LED */

	ret_val = mac->ops.id_led_init(hw);

	/* An error is not fatal and we should not stop init due to this */

	if (ret_val)

		e_dbg("Error initializing identification LED\n");

		/* This is not fatal and we should not stop init due to this */



	/* Disabling VLAN filtering */

	e_dbg("Initializing the IEEE VLAN\n");
@@ -784,14 +784,14 @@ static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw) 


	/* Set the transmit descriptor write-back policy */

	reg_data = er32(TXDCTL(0));

	reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |

		   E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;

	reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |

		    E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);

	ew32(TXDCTL(0), reg_data);



	/* ...for both queues. */

	reg_data = er32(TXDCTL(1));

	reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |

		   E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;

	reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |

		    E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);

	ew32(TXDCTL(1), reg_data);



	/* Enable retransmit on late collisions */
@@ -818,10 +818,9 @@ static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw) 
	/* default to true to enable the MDIC W/A */

	hw->dev_spec.e80003es2lan.mdic_wa_enable = true;



	ret_val = e1000_read_kmrn_reg_80003es2lan(hw,

	                              E1000_KMRNCTRLSTA_OFFSET >>

	                              E1000_KMRNCTRLSTA_OFFSET_SHIFT,

	                              &i);

	ret_val =

	    e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_OFFSET >>

					    E1000_KMRNCTRLSTA_OFFSET_SHIFT, &i);

	if (!ret_val) {

		if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==

		    E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO)
@@ -891,7 +890,7 @@ static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw) 
{

	struct e1000_phy_info *phy = &hw->phy;

	s32 ret_val;

	u32 ctrl_ext;

	u32 reg;

	u16 data;



	ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
@@ -954,22 +953,19 @@ static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw) 
	}



	/* Bypass Rx and Tx FIFO's */

	ret_val = e1000_write_kmrn_reg_80003es2lan(hw,

					E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL,

					E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |

	reg = E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL;

	data = (E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |

		E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);

	ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);

	if (ret_val)

		return ret_val;



	ret_val = e1000_read_kmrn_reg_80003es2lan(hw,

				       E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,

				       &data);

	reg = E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE;

	ret_val = e1000_read_kmrn_reg_80003es2lan(hw, reg, &data);

	if (ret_val)

		return ret_val;

	data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;

	ret_val = e1000_write_kmrn_reg_80003es2lan(hw,

					E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,

					data);

	ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);

	if (ret_val)

		return ret_val;
@@ -982,9 +978,9 @@ static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw) 
	if (ret_val)

		return ret_val;



	ctrl_ext = er32(CTRL_EXT);

	ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);

	ew32(CTRL_EXT, ctrl_ext);

	reg = er32(CTRL_EXT);

	reg &= ~E1000_CTRL_EXT_LINK_MODE_MASK;

	ew32(CTRL_EXT, reg);



	ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);

	if (ret_val)
@@ -1061,13 +1057,15 @@ static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw) 
						   reg_data);

	if (ret_val)

		return ret_val;

	ret_val = e1000_read_kmrn_reg_80003es2lan(hw,

	ret_val =

	    e1000_read_kmrn_reg_80003es2lan(hw,

					    E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,

					    &reg_data);

	if (ret_val)

		return ret_val;

	reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;

	ret_val = e1000_write_kmrn_reg_80003es2lan(hw,

	ret_val =

	    e1000_write_kmrn_reg_80003es2lan(hw,

					     E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,

					     reg_data);

	if (ret_val)
@@ -1125,7 +1123,8 @@ static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex) 
	u16 reg_data, reg_data2;



	reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;

	ret_val = e1000_write_kmrn_reg_80003es2lan(hw,

	ret_val =

	    e1000_write_kmrn_reg_80003es2lan(hw,

					     E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,

					     reg_data);

	if (ret_val)
@@ -1171,7 +1170,8 @@ static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw) 
	u32 i = 0;



	reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;

	ret_val = e1000_write_kmrn_reg_80003es2lan(hw,

	ret_val =

	    e1000_write_kmrn_reg_80003es2lan(hw,

					     E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,

					     reg_data);

	if (ret_val)
@@ -1419,4 +1419,3 @@ const struct e1000_info e1000_es2_info = { 
	.phy_ops		= &es2_phy_ops,

	.nvm_ops		= &es2_nvm_ops,

};

drivers/net/ethernet/intel/e1000e/82571.c

+18 −20
Original line number Diff line number Diff line
@@ -437,7 +437,7 @@ static s32 e1000_get_phy_id_82571(struct e1000_hw *hw) 
			return ret_val;



		phy->id = (u32)(phy_id << 16);

		udelay(20);

		usleep_range(20, 40);

		ret_val = e1e_rphy(hw, MII_PHYSID2, &phy_id);

		if (ret_val)

			return ret_val;
@@ -482,7 +482,7 @@ static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) 
		if (!(swsm & E1000_SWSM_SMBI))

			break;



		udelay(50);

		usleep_range(50, 100);

		i++;

	}
@@ -499,7 +499,7 @@ static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) 
		if (er32(SWSM) & E1000_SWSM_SWESMBI)

			break;



		udelay(50);

		usleep_range(50, 100);

	}



	if (i == fw_timeout) {
@@ -526,6 +526,7 @@ static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw) 
	swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);

	ew32(SWSM, swsm);

}



/**

 *  e1000_get_hw_semaphore_82573 - Acquire hardware semaphore

 *  @hw: pointer to the HW structure
@@ -846,9 +847,9 @@ static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, 
	}



	for (i = 0; i < words; i++) {

		eewr = (data[i] << E1000_NVM_RW_REG_DATA) |

		eewr = ((data[i] << E1000_NVM_RW_REG_DATA) |

			((offset + i) << E1000_NVM_RW_ADDR_SHIFT) |

		       E1000_NVM_RW_REG_START;

			E1000_NVM_RW_REG_START);



		ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);

		if (ret_val)
@@ -875,8 +876,7 @@ static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw) 
	s32 timeout = PHY_CFG_TIMEOUT;



	while (timeout) {

		if (er32(EEMNGCTL) &

		    E1000_NVM_CFG_DONE_PORT_0)

		if (er32(EEMNGCTL) & E1000_NVM_CFG_DONE_PORT_0)

			break;

		usleep_range(1000, 2000);

		timeout--;
@@ -1022,7 +1022,7 @@ static s32 e1000_reset_hw_82571(struct e1000_hw *hw) 
	}



	if (hw->nvm.type == e1000_nvm_flash_hw) {

		udelay(10);

		usleep_range(10, 20);

		ctrl_ext = er32(CTRL_EXT);

		ctrl_ext |= E1000_CTRL_EXT_EE_RST;

		ew32(CTRL_EXT, ctrl_ext);
@@ -1095,9 +1095,9 @@ static s32 e1000_init_hw_82571(struct e1000_hw *hw) 


	/* Initialize identification LED */

	ret_val = mac->ops.id_led_init(hw);

	/* An error is not fatal and we should not stop init due to this */

	if (ret_val)

		e_dbg("Error initializing identification LED\n");

		/* This is not fatal and we should not stop init due to this */



	/* Disabling VLAN filtering */

	e_dbg("Initializing the IEEE VLAN\n");
@@ -1122,9 +1122,8 @@ static s32 e1000_init_hw_82571(struct e1000_hw *hw) 


	/* Set the transmit descriptor write-back policy */

	reg_data = er32(TXDCTL(0));

	reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |

		   E1000_TXDCTL_FULL_TX_DESC_WB |

		   E1000_TXDCTL_COUNT_DESC;

	reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |

		    E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);

	ew32(TXDCTL(0), reg_data);



	/* ...for both queues. */
@@ -1140,9 +1139,9 @@ static s32 e1000_init_hw_82571(struct e1000_hw *hw) 
		break;

	default:

		reg_data = er32(TXDCTL(1));

		reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |

		reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |

			    E1000_TXDCTL_FULL_TX_DESC_WB |

			   E1000_TXDCTL_COUNT_DESC;

			    E1000_TXDCTL_COUNT_DESC);

		ew32(TXDCTL(1), reg_data);

		break;

	}
@@ -1530,7 +1529,7 @@ static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw) 
	status = er32(STATUS);

	er32(RXCW);

	/* SYNCH bit and IV bit are sticky */

	udelay(10);

	usleep_range(10, 20);

	rxcw = er32(RXCW);



	if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
@@ -1633,7 +1632,7 @@ static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw) 
			 * the IV bit and restart Autoneg

			 */

			for (i = 0; i < AN_RETRY_COUNT; i++) {

				udelay(10);

				usleep_range(10, 20);

				rxcw = er32(RXCW);

				if ((rxcw & E1000_RXCW_SYNCH) &&

				    (rxcw & E1000_RXCW_C))
@@ -2066,4 +2065,3 @@ const struct e1000_info e1000_82583_info = { 
	.phy_ops		= &e82_phy_ops_bm,

	.nvm_ops		= &e82571_nvm_ops,

};

drivers/net/ethernet/intel/e1000e/82571.h

+2 −0
Original line number Diff line number Diff line
@@ -44,6 +44,8 @@ 
#define E1000_EIAC_82574	0x000DC	/* Ext. Interrupt Auto Clear - RW */

#define E1000_EIAC_MASK_82574	0x01F00000



#define E1000_IVAR_INT_ALLOC_VALID	0x8



/* Manageability Operation Mode mask */

#define E1000_NVM_INIT_CTRL2_MNGM	0x6000

drivers/net/ethernet/intel/e1000e/defines.h

+14 −11
Original line number Diff line number Diff line
@@ -66,7 +66,7 @@ 
#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES  0x00C00000

#define E1000_CTRL_EXT_EIAME          0x01000000

#define E1000_CTRL_EXT_DRV_LOAD       0x10000000 /* Driver loaded bit for FW */

#define E1000_CTRL_EXT_IAME           0x08000000 /* Interrupt acknowledge Auto-mask */

#define E1000_CTRL_EXT_IAME		0x08000000 /* Int ACK Auto-mask */

#define E1000_CTRL_EXT_PBA_CLR        0x80000000 /* PBA Clear */

#define E1000_CTRL_EXT_LSECCK         0x00001000

#define E1000_CTRL_EXT_PHYPDEN        0x00100000
@@ -216,6 +216,8 @@ 
#define E1000_CTRL_MEHE     0x00080000  /* Memory Error Handling Enable */

#define E1000_CTRL_SWDPIN0  0x00040000  /* SWDPIN 0 value */

#define E1000_CTRL_SWDPIN1  0x00080000  /* SWDPIN 1 value */

#define E1000_CTRL_ADVD3WUC 0x00100000  /* D3 WUC */

#define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 /* PHY PM enable */

#define E1000_CTRL_SWDPIO0  0x00400000  /* SWDPIN 0 Input or output */

#define E1000_CTRL_RST      0x04000000  /* Global reset */

#define E1000_CTRL_RFCE     0x08000000  /* Receive Flow Control enable */
@@ -239,12 +241,11 @@ 
#define E1000_STATUS_SPEED_1000 0x00000080      /* Speed 1000Mb/s */

#define E1000_STATUS_LAN_INIT_DONE 0x00000200   /* Lan Init Completion by NVM */

#define E1000_STATUS_PHYRA      0x00000400      /* PHY Reset Asserted */

#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */

#define E1000_STATUS_GIO_MASTER_ENABLE	0x00080000	/* Master Req status */



#define HALF_DUPLEX 1

#define FULL_DUPLEX 2





#define ADVERTISE_10_HALF                 0x0001

#define ADVERTISE_10_FULL                 0x0002

#define ADVERTISE_100_HALF                0x0004
@@ -311,6 +312,7 @@ 


/* SerDes Control */

#define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400

#define E1000_SCTL_ENABLE_SERDES_LOOPBACK	0x0410



/* Receive Checksum Control */

#define E1000_RXCSUM_TUOFL     0x00000200   /* TCP / UDP checksum offload */
@@ -400,7 +402,8 @@ 
#define E1000_ICR_RXDMT0        0x00000010 /* Rx desc min. threshold (0) */

#define E1000_ICR_RXT0          0x00000080 /* Rx timer intr (ring 0) */

#define E1000_ICR_ECCER         0x00400000 /* Uncorrectable ECC Error */

#define E1000_ICR_INT_ASSERTED  0x80000000 /* If this bit asserted, the driver should claim the interrupt */

/* If this bit asserted, the driver should claim the interrupt */

#define E1000_ICR_INT_ASSERTED	0x80000000

#define E1000_ICR_RXQ0          0x00100000 /* Rx Queue 0 Interrupt */

#define E1000_ICR_RXQ1          0x00200000 /* Rx Queue 1 Interrupt */

#define E1000_ICR_TXQ0          0x00400000 /* Tx Queue 0 Interrupt */
@@ -583,12 +586,12 @@ 
#define E1000_EECD_SEC1VAL   0x00400000 /* Sector One Valid */

#define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES)



#define E1000_NVM_RW_REG_DATA   16   /* Offset to data in NVM read/write registers */

#define E1000_NVM_RW_REG_DATA	16	/* Offset to data in NVM r/w regs */

#define E1000_NVM_RW_REG_DONE	2	/* Offset to READ/WRITE done bit */

#define E1000_NVM_RW_REG_START	1	/* Start operation */

#define E1000_NVM_RW_ADDR_SHIFT	2	/* Shift to the address bits */

#define E1000_NVM_POLL_WRITE    1    /* Flag for polling for write complete */

#define E1000_NVM_POLL_READ     0    /* Flag for polling for read complete */

#define E1000_NVM_POLL_WRITE	1	/* Flag for polling write complete */

#define E1000_NVM_POLL_READ	0	/* Flag for polling read complete */

#define E1000_FLASH_UPDATES	2000



/* NVM Word Offsets */

drivers/net/ethernet/intel/e1000e/e1000.h

+9 −9
Original line number Diff line number Diff line
@@ -61,7 +61,6 @@ struct e1000_info; 
#define e_notice(format, arg...) \

	netdev_notice(adapter->netdev, format, ## arg)





/* Interrupt modes, as used by the IntMode parameter */

#define E1000E_INT_MODE_LEGACY		0

#define E1000E_INT_MODE_MSI		1
@@ -239,9 +238,8 @@ struct e1000_adapter { 
	u16 tx_itr;

	u16 rx_itr;



	/* Tx */

	struct e1000_ring *tx_ring /* One per active queue */

						____cacheline_aligned_in_smp;

	/* Tx - one ring per active queue */

	struct e1000_ring *tx_ring ____cacheline_aligned_in_smp;

	u32 tx_fifo_limit;



	struct napi_struct napi;
@@ -558,12 +556,14 @@ static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw) 
	return hw->nvm.ops.update(hw);

}



static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)

static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words,

				 u16 *data)

{

	return hw->nvm.ops.read(hw, offset, words, data);

}



static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)

static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words,

				  u16 *data)

{

	return hw->nvm.ops.write(hw, offset, words, data);

}
@@ -597,7 +597,7 @@ static inline s32 __ew32_prepare(struct e1000_hw *hw) 
	s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT;



	while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i)

		udelay(50);

		usleep_range(50, 100);



	return i;

}