Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 0af62b01 authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
Browse files

drm/radeon/kms: add ucode loader for NI 



The MC ucode is no longer loaded by the vbios
tables as on previous asics.  It now must be loaded
by the driver.

Signed-off-by: default avatarAlex Deucher <alexdeucher@gmail.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent fee298fd

drivers/gpu/drm/radeon/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -66,7 +66,7 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \ 
	r200.o radeon_legacy_tv.o r600_cs.o r600_blit.o r600_blit_shaders.o \

	r600_blit_kms.o radeon_pm.o atombios_dp.o r600_audio.o r600_hdmi.o \

	evergreen.o evergreen_cs.o evergreen_blit_shaders.o evergreen_blit_kms.o \

	radeon_trace_points.o

	radeon_trace_points.o ni.o



radeon-$(CONFIG_COMPAT) += radeon_ioc32.o

radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o

drivers/gpu/drm/radeon/evergreen.c

+18 −3
Original line number Diff line number Diff line
@@ -2855,6 +2855,20 @@ static int evergreen_startup(struct radeon_device *rdev) 
	/* enable pcie gen2 link */

	evergreen_pcie_gen2_enable(rdev);



	if (ASIC_IS_DCE5(rdev)) {

		if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {

			r = ni_init_microcode(rdev);

			if (r) {

				DRM_ERROR("Failed to load firmware!\n");

				return r;

			}

		}

		r = btc_mc_load_microcode(rdev);

		if (r) {

			DRM_ERROR("Failed to load MC firmware!\n");

			return r;

		}

	} else {

		if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {

			r = r600_init_microcode(rdev);

			if (r) {
@@ -2862,6 +2876,7 @@ static int evergreen_startup(struct radeon_device *rdev) 
				return r;

			}

		}

	}



	evergreen_mc_program(rdev);

	if (rdev->flags & RADEON_IS_AGP) {

drivers/gpu/drm/radeon/ni.c

0 → 100644
+316 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2010 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: Alex Deucher

 */

#include <linux/firmware.h>

#include <linux/platform_device.h>

#include <linux/slab.h>

#include "drmP.h"

#include "radeon.h"

#include "radeon_asic.h"

#include "radeon_drm.h"

#include "nid.h"

#include "atom.h"

#include "ni_reg.h"



#define EVERGREEN_PFP_UCODE_SIZE 1120

#define EVERGREEN_PM4_UCODE_SIZE 1376

#define EVERGREEN_RLC_UCODE_SIZE 768

#define BTC_MC_UCODE_SIZE 6024



/* Firmware Names */

MODULE_FIRMWARE("radeon/BARTS_pfp.bin");

MODULE_FIRMWARE("radeon/BARTS_me.bin");

MODULE_FIRMWARE("radeon/BARTS_mc.bin");

MODULE_FIRMWARE("radeon/BTC_rlc.bin");

MODULE_FIRMWARE("radeon/TURKS_pfp.bin");

MODULE_FIRMWARE("radeon/TURKS_me.bin");

MODULE_FIRMWARE("radeon/TURKS_mc.bin");

MODULE_FIRMWARE("radeon/CAICOS_pfp.bin");

MODULE_FIRMWARE("radeon/CAICOS_me.bin");

MODULE_FIRMWARE("radeon/CAICOS_mc.bin");



#define BTC_IO_MC_REGS_SIZE 29



static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {

	{0x00000077, 0xff010100},

	{0x00000078, 0x00000000},

	{0x00000079, 0x00001434},

	{0x0000007a, 0xcc08ec08},

	{0x0000007b, 0x00040000},

	{0x0000007c, 0x000080c0},

	{0x0000007d, 0x09000000},

	{0x0000007e, 0x00210404},

	{0x00000081, 0x08a8e800},

	{0x00000082, 0x00030444},

	{0x00000083, 0x00000000},

	{0x00000085, 0x00000001},

	{0x00000086, 0x00000002},

	{0x00000087, 0x48490000},

	{0x00000088, 0x20244647},

	{0x00000089, 0x00000005},

	{0x0000008b, 0x66030000},

	{0x0000008c, 0x00006603},

	{0x0000008d, 0x00000100},

	{0x0000008f, 0x00001c0a},

	{0x00000090, 0xff000001},

	{0x00000094, 0x00101101},

	{0x00000095, 0x00000fff},

	{0x00000096, 0x00116fff},

	{0x00000097, 0x60010000},

	{0x00000098, 0x10010000},

	{0x00000099, 0x00006000},

	{0x0000009a, 0x00001000},

	{0x0000009f, 0x00946a00}

};



static const u32 turks_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {

	{0x00000077, 0xff010100},

	{0x00000078, 0x00000000},

	{0x00000079, 0x00001434},

	{0x0000007a, 0xcc08ec08},

	{0x0000007b, 0x00040000},

	{0x0000007c, 0x000080c0},

	{0x0000007d, 0x09000000},

	{0x0000007e, 0x00210404},

	{0x00000081, 0x08a8e800},

	{0x00000082, 0x00030444},

	{0x00000083, 0x00000000},

	{0x00000085, 0x00000001},

	{0x00000086, 0x00000002},

	{0x00000087, 0x48490000},

	{0x00000088, 0x20244647},

	{0x00000089, 0x00000005},

	{0x0000008b, 0x66030000},

	{0x0000008c, 0x00006603},

	{0x0000008d, 0x00000100},

	{0x0000008f, 0x00001c0a},

	{0x00000090, 0xff000001},

	{0x00000094, 0x00101101},

	{0x00000095, 0x00000fff},

	{0x00000096, 0x00116fff},

	{0x00000097, 0x60010000},

	{0x00000098, 0x10010000},

	{0x00000099, 0x00006000},

	{0x0000009a, 0x00001000},

	{0x0000009f, 0x00936a00}

};



static const u32 caicos_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {

	{0x00000077, 0xff010100},

	{0x00000078, 0x00000000},

	{0x00000079, 0x00001434},

	{0x0000007a, 0xcc08ec08},

	{0x0000007b, 0x00040000},

	{0x0000007c, 0x000080c0},

	{0x0000007d, 0x09000000},

	{0x0000007e, 0x00210404},

	{0x00000081, 0x08a8e800},

	{0x00000082, 0x00030444},

	{0x00000083, 0x00000000},

	{0x00000085, 0x00000001},

	{0x00000086, 0x00000002},

	{0x00000087, 0x48490000},

	{0x00000088, 0x20244647},

	{0x00000089, 0x00000005},

	{0x0000008b, 0x66030000},

	{0x0000008c, 0x00006603},

	{0x0000008d, 0x00000100},

	{0x0000008f, 0x00001c0a},

	{0x00000090, 0xff000001},

	{0x00000094, 0x00101101},

	{0x00000095, 0x00000fff},

	{0x00000096, 0x00116fff},

	{0x00000097, 0x60010000},

	{0x00000098, 0x10010000},

	{0x00000099, 0x00006000},

	{0x0000009a, 0x00001000},

	{0x0000009f, 0x00916a00}

};



int btc_mc_load_microcode(struct radeon_device *rdev)

{

	const __be32 *fw_data;

	u32 mem_type, running, blackout = 0;

	u32 *io_mc_regs;

	int i;



	if (!rdev->mc_fw)

		return -EINVAL;



	switch (rdev->family) {

	case CHIP_BARTS:

		io_mc_regs = (u32 *)&barts_io_mc_regs;

		break;

	case CHIP_TURKS:

		io_mc_regs = (u32 *)&turks_io_mc_regs;

		break;

	case CHIP_CAICOS:

	default:

		io_mc_regs = (u32 *)&caicos_io_mc_regs;

		break;

	}



	mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT;

	running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;



	if ((mem_type == MC_SEQ_MISC0_GDDR5_VALUE) && (running == 0)) {

		if (running) {

			blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);

			WREG32(MC_SHARED_BLACKOUT_CNTL, 1);

		}



		/* reset the engine and set to writable */

		WREG32(MC_SEQ_SUP_CNTL, 0x00000008);

		WREG32(MC_SEQ_SUP_CNTL, 0x00000010);



		/* load mc io regs */

		for (i = 0; i < BTC_IO_MC_REGS_SIZE; i++) {

			WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);

			WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);

		}

		/* load the MC ucode */

		fw_data = (const __be32 *)rdev->mc_fw->data;

		for (i = 0; i < BTC_MC_UCODE_SIZE; i++)

			WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));



		/* put the engine back into the active state */

		WREG32(MC_SEQ_SUP_CNTL, 0x00000008);

		WREG32(MC_SEQ_SUP_CNTL, 0x00000004);

		WREG32(MC_SEQ_SUP_CNTL, 0x00000001);



		/* wait for training to complete */

		while (!(RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD))

			udelay(10);



		if (running)

			WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);

	}



	return 0;

}



int ni_init_microcode(struct radeon_device *rdev)

{

	struct platform_device *pdev;

	const char *chip_name;

	const char *rlc_chip_name;

	size_t pfp_req_size, me_req_size, rlc_req_size, mc_req_size;

	char fw_name[30];

	int err;



	DRM_DEBUG("\n");



	pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);

	err = IS_ERR(pdev);

	if (err) {

		printk(KERN_ERR "radeon_cp: Failed to register firmware\n");

		return -EINVAL;

	}



	switch (rdev->family) {

	case CHIP_BARTS:

		chip_name = "BARTS";

		rlc_chip_name = "BTC";

		break;

	case CHIP_TURKS:

		chip_name = "TURKS";

		rlc_chip_name = "BTC";

		break;

	case CHIP_CAICOS:

		chip_name = "CAICOS";

		rlc_chip_name = "BTC";

		break;

	default: BUG();

	}



	pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;

	me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;

	rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;

	mc_req_size = BTC_MC_UCODE_SIZE * 4;



	DRM_INFO("Loading %s Microcode\n", chip_name);



	snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);

	err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);

	if (err)

		goto out;

	if (rdev->pfp_fw->size != pfp_req_size) {

		printk(KERN_ERR

		       "ni_cp: Bogus length %zu in firmware \"%s\"\n",

		       rdev->pfp_fw->size, fw_name);

		err = -EINVAL;

		goto out;

	}



	snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);

	err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);

	if (err)

		goto out;

	if (rdev->me_fw->size != me_req_size) {

		printk(KERN_ERR

		       "ni_cp: Bogus length %zu in firmware \"%s\"\n",

		       rdev->me_fw->size, fw_name);

		err = -EINVAL;

	}



	snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);

	err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);

	if (err)

		goto out;

	if (rdev->rlc_fw->size != rlc_req_size) {

		printk(KERN_ERR

		       "ni_rlc: Bogus length %zu in firmware \"%s\"\n",

		       rdev->rlc_fw->size, fw_name);

		err = -EINVAL;

	}



	snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);

	err = request_firmware(&rdev->mc_fw, fw_name, &pdev->dev);

	if (err)

		goto out;

	if (rdev->mc_fw->size != mc_req_size) {

		printk(KERN_ERR

		       "ni_mc: Bogus length %zu in firmware \"%s\"\n",

		       rdev->mc_fw->size, fw_name);

		err = -EINVAL;

	}

out:

	platform_device_unregister(pdev);



	if (err) {

		if (err != -EINVAL)

			printk(KERN_ERR

			       "ni_cp: Failed to load firmware \"%s\"\n",

			       fw_name);

		release_firmware(rdev->pfp_fw);

		rdev->pfp_fw = NULL;

		release_firmware(rdev->me_fw);

		rdev->me_fw = NULL;

		release_firmware(rdev->rlc_fw);

		rdev->rlc_fw = NULL;

		release_firmware(rdev->mc_fw);

		rdev->mc_fw = NULL;

	}

	return err;

}

drivers/gpu/drm/radeon/nid.h

0 → 100644
+41 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2010 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: Alex Deucher

 */

#ifndef NI_H

#define NI_H



#define MC_SHARED_BLACKOUT_CNTL           		0x20ac

#define MC_SEQ_SUP_CNTL           			0x28c8

#define		RUN_MASK      				(1 << 0)

#define MC_SEQ_SUP_PGM           			0x28cc

#define MC_IO_PAD_CNTL_D0           			0x29d0

#define		MEM_FALL_OUT_CMD      			(1 << 8)

#define MC_SEQ_MISC0           				0x2a00

#define		MC_SEQ_MISC0_GDDR5_SHIFT      		28

#define		MC_SEQ_MISC0_GDDR5_MASK      		0xf0000000

#define		MC_SEQ_MISC0_GDDR5_VALUE      		5

#define MC_SEQ_IO_DEBUG_INDEX           		0x2a44

#define MC_SEQ_IO_DEBUG_DATA           			0x2a48



#endif

drivers/gpu/drm/radeon/radeon.h

+4 −0
Original line number Diff line number Diff line
@@ -1152,6 +1152,7 @@ struct radeon_device { 
	const struct firmware *me_fw;	/* all family ME firmware */

	const struct firmware *pfp_fw;	/* r6/700 PFP firmware */

	const struct firmware *rlc_fw;	/* r6/700 RLC firmware */

	const struct firmware *mc_fw;	/* NI MC firmware */

	struct r600_blit r600_blit;

	struct r700_vram_scratch vram_scratch;

	int msi_enabled; /* msi enabled */
@@ -1561,6 +1562,9 @@ extern int evergreen_irq_set(struct radeon_device *rdev); 
extern int evergreen_blit_init(struct radeon_device *rdev);

extern void evergreen_blit_fini(struct radeon_device *rdev);



extern int ni_init_microcode(struct radeon_device *rdev);

extern int btc_mc_load_microcode(struct radeon_device *rdev);



/* radeon_acpi.c */ 

#if defined(CONFIG_ACPI) 

extern int radeon_acpi_init(struct radeon_device *rdev);