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Commit 09f3b37e authored by Vineet Gupta's avatar Vineet Gupta
Browse files

ARC: entry.S: Introduce INTERRUPT_{PROLOGUE,EPILOGUE} 



-common'ize macros for level 1 and level 2 interrupts

Signed-off-by: default avatarVineet Gupta <vgupta@synopsys.com>
parent fbfa26ae

arch/arc/include/asm/arcregs.h

+0 −3
Original line number Diff line number Diff line
@@ -76,9 +76,6 @@ 
#define ECR_C_BIT_DTLB_LD_MISS		8

#define ECR_C_BIT_DTLB_ST_MISS		9



/* Dummy ECR values for Interrupts */

#define event_IRQ1		0x0031abcd

#define event_IRQ2		0x0032abcd



/* Auxiliary registers */

#define AUX_IDENTITY		4

arch/arc/include/asm/entry.h

+19 −58
Original line number Diff line number Diff line
@@ -465,55 +465,37 @@ 
	/* orig_r0, ECR, user_r25 skipped automatically */

.endm



/* Dummy ECR values for Interrupts */

#define event_IRQ1		0x0031abcd

#define event_IRQ2		0x0032abcd



/*--------------------------------------------------------------

 * Save all registers used by interrupt handlers.

 *-------------------------------------------------------------*/

.macro SAVE_ALL_INT1

.macro INTERRUPT_PROLOGUE  LVL



	/* restore original r9 */

	PROLOG_RESTORE_REG  r9, @int1_saved_reg

	/* free up r9 as scratchpad */

	PROLOG_FREEUP_REG r9, @int\LVL\()_saved_reg



	/* now we are ready to save the remaining context :) */

	st      event_IRQ1, [sp, 8]    /* Dummy ECR */

	st      0, [sp, 4]    /* orig_r0 , N/A for IRQ */

	/* Which mode (user/kernel) was the system in when intr occurred */

	lr  r9, [status32_l\LVL\()]



	SAVE_R0_TO_R12

	PUSH	gp

	PUSH	fp

	PUSH	blink

	PUSH	ilink1

	PUSHAX	status32_l1

	PUSH	lp_count

	PUSHAX	lp_end

	PUSHAX	lp_start

	PUSHAX	bta_l1

.endm



.macro SAVE_ALL_INT2

	SWITCH_TO_KERNEL_STK



	/*

	 * In SMP we can't use mem nor can we use SCRARCH_DATA0

	 * as we do for int1 because int2 can clobber it

	 * Hence 2 levels of intr are NOT allowed in SMP (by Kconfig)

	 */

	/* restore original r9 */

	PROLOG_RESTORE_REG r9, @int2_saved_reg

	PROLOG_RESTORE_REG  r9, @int\LVL\()_saved_reg



	/* now we are ready to save the remaining context :) */

	st      event_IRQ2, [sp, 8]    /* Dummy ECR */

	/* now we are ready to save the remaining context */

	st      0x003\LVL\()abcd, [sp, 8]    /* Dummy ECR */

	st      0, [sp, 4]    /* orig_r0 , N/A for IRQ */



	SAVE_R0_TO_R12

	PUSH	gp

	PUSH	fp

	PUSH	blink

	PUSH	ilink2

	PUSHAX	status32_l2

	PUSH	ilink\LVL\()

	PUSHAX	status32_l\LVL\()

	PUSH	lp_count

	PUSHAX	lp_end

	PUSHAX	lp_start

	PUSHAX	bta_l2

	PUSHAX	bta_l\LVL\()

.endm



/*--------------------------------------------------------------
@@ -525,17 +507,16 @@ 
 * for memory load operations. If used in that way interrupts are deffered

 * by hardware and that is not good.

 *-------------------------------------------------------------*/



.macro RESTORE_ALL_INT1

	POPAX	bta_l1

.macro INTERRUPT_EPILOGUE  LVL

	POPAX	bta_l\LVL\()

	POPAX	lp_start

	POPAX	lp_end



	POP	r9

	mov	lp_count, r9	;LD to lp_count is not allowed



	POPAX	status32_l1

	POP	ilink1

	POPAX	status32_l\LVL\()

	POP	ilink\LVL\()

	POP	blink

	POP	fp

	POP	gp
@@ -545,26 +526,6 @@ 
	/* orig_r0, ECR, user_r25 skipped automatically */

.endm



.macro RESTORE_ALL_INT2

	POPAX	bta_l2

	POPAX	lp_start

	POPAX	lp_end



	POP	r9

	mov	lp_count, r9	;LD to lp_count is not allowed



	POPAX	status32_l2

	POP	ilink2

	POP	blink

	POP	fp

	POP	gp

	RESTORE_R12_TO_R0



	ld  sp, [sp] /* restore original sp */

	/* orig_r0, ECR, user_r25 skipped automatically */

.endm





/* Get CPU-ID of this core */

.macro  GET_CPU_ID  reg

	lr  \reg, [identity]

arch/arc/kernel/entry.S

+4 −18
Original line number Diff line number Diff line
@@ -186,14 +186,7 @@ reserved: ; processor restart 
; ---------------------------------------------

ENTRY(handle_interrupt_level2)



	; free up r9 as scratchpad

	PROLOG_FREEUP_REG r9, @int2_saved_reg



	;Which mode (user/kernel) was the system in when intr occured

	lr  r9, [status32_l2]



	SWITCH_TO_KERNEL_STK

	SAVE_ALL_INT2

	INTERRUPT_PROLOGUE 2



	;------------------------------------------------------

	; if L2 IRQ interrupted a L1 ISR, disable preemption
@@ -233,13 +226,7 @@ END(handle_interrupt_level2) 
; ---------------------------------------------

ENTRY(handle_interrupt_level1)



	PROLOG_FREEUP_REG r9, @int1_saved_reg



	;Which mode (user/kernel) was the system in when intr occured

	lr  r9, [status32_l1]



	SWITCH_TO_KERNEL_STK

	SAVE_ALL_INT1

	INTERRUPT_PROLOGUE 1



	lr  r0, [icause1]

	and r0, r0, 0x1f
@@ -698,7 +685,7 @@ not_exception: 


149:

	;return from level 2

	RESTORE_ALL_INT2

	INTERRUPT_EPILOGUE 2

debug_marker_l2:

	rtie
@@ -709,8 +696,7 @@ not_level2_interrupt: 
	bbit0  r10, STATUS_A1_BIT, not_level1_interrupt



	;return from level 1



	RESTORE_ALL_INT1

	INTERRUPT_EPILOGUE 1

debug_marker_l1:

	rtie