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Commit 097f70b3 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus 

Pull MIPS fixes from Ralf Baechle:
 - Properly setup irq handling for ATH79 platforms
 - Fix bootmem mapstart calculation for contiguous maps
 - Handle little endian and older CPUs correct in BPF
 - Fix console for Fulong 2E systems
 - Handle FTLB correctly on R6 CPUs
 - Fixes for CM, GIC and MAAR support code

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
  MIPS: Initialise MAARs on secondary CPUs
  MIPS: print MAAR configuration during boot
  MIPS: mm: compile maar_init unconditionally
  irqchip: mips-gic: Fix pending & mask reads for MIPS64 with 32b GIC.
  irqchip: mips-gic: Convert CPU numbers to VP IDs.
  MIPS: CM: Provide a function to map from CPU to VP ID.
  MIPS: Fix FTLB detection for R6
  MIPS: cpu-features: Add cpu_has_ftlb
  MIPS: ATH79: Add irq chip ar7240-misc-intc
  MIPS: ATH79: Set missing irq ack handler for ar7100-misc-intc irq chip
  MIPS: BPF: Fix build on pre-R2 little endian CPUs
  MIPS: BPF: Avoid unreachable code on little endian
  MIPS: bootmem: Fix mapstart calculation for contiguous maps
  MIPS: Fix console output for Fulong2e system
parents e3be4266 e060f6ed

Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt

+18 −2
Original line number Diff line number Diff line
@@ -4,8 +4,8 @@ The MISC interrupt controller is a secondary controller for lower priority 
interrupt.



Required Properties:

- compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-misc-intc"

  as fallback

- compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-misc-intc" or

  "qca,<soctype>-cpu-intc", "qca,ar7240-misc-intc"

- reg: Base address and size of the controllers memory area

- interrupt-parent: phandle of the parent interrupt controller.

- interrupts: Interrupt specifier for the controllers interrupt.
@@ -13,6 +13,9 @@ Required Properties: 
- #interrupt-cells : Specifies the number of cells needed to encode interrupt

		     source, should be 1



Compatible fallback depends on the SoC. Use ar7100 for ar71xx and ar913x,

use ar7240 for all other SoCs.



Please refer to interrupts.txt in this directory for details of the common

Interrupt Controllers bindings used by client devices.
@@ -28,3 +31,16 @@ Example: 
		interrupt-controller;

		#interrupt-cells = <1>;

	};



Another example:



	interrupt-controller@18060010 {

		compatible = "qca,ar9331-misc-intc", qca,ar7240-misc-intc";

		reg = <0x18060010 0x4>;



		interrupt-parent = <&cpuintc>;

		interrupts = <6>;



		interrupt-controller;

		#interrupt-cells = <1>;

	};

arch/mips/ath79/irq.c

+20 −2
Original line number Diff line number Diff line
@@ -293,8 +293,26 @@ static int __init ath79_misc_intc_of_init( 


	return 0;

}

IRQCHIP_DECLARE(ath79_misc_intc, "qca,ar7100-misc-intc",

		ath79_misc_intc_of_init);



static int __init ar7100_misc_intc_of_init(

	struct device_node *node, struct device_node *parent)

{

	ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;

	return ath79_misc_intc_of_init(node, parent);

}



IRQCHIP_DECLARE(ar7100_misc_intc, "qca,ar7100-misc-intc",

		ar7100_misc_intc_of_init);



static int __init ar7240_misc_intc_of_init(

	struct device_node *node, struct device_node *parent)

{

	ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;

	return ath79_misc_intc_of_init(node, parent);

}



IRQCHIP_DECLARE(ar7240_misc_intc, "qca,ar7240-misc-intc",

		ar7240_misc_intc_of_init);



static int __init ar79_cpu_intc_of_init(

	struct device_node *node, struct device_node *parent)

arch/mips/include/asm/cpu-features.h

+3 −0
Original line number Diff line number Diff line
@@ -20,6 +20,9 @@ 
#ifndef cpu_has_tlb

#define cpu_has_tlb		(cpu_data[0].options & MIPS_CPU_TLB)

#endif

#ifndef cpu_has_ftlb

#define cpu_has_ftlb		(cpu_data[0].options & MIPS_CPU_FTLB)

#endif

#ifndef cpu_has_tlbinv

#define cpu_has_tlbinv		(cpu_data[0].options & MIPS_CPU_TLBINV)

#endif

arch/mips/include/asm/cpu.h

+1 −0
Original line number Diff line number Diff line
@@ -385,6 +385,7 @@ enum cpu_type_enum { 
#define MIPS_CPU_CDMM		0x4000000000ull	/* CPU has Common Device Memory Map */

#define MIPS_CPU_BP_GHIST	0x8000000000ull /* R12K+ Branch Prediction Global History */

#define MIPS_CPU_SP		0x10000000000ull /* Small (1KB) page support */

#define MIPS_CPU_FTLB		0x20000000000ull /* CPU has Fixed-page-size TLB */



/*

 * CPU ASE encodings

arch/mips/include/asm/maar.h

+9 −0
Original line number Diff line number Diff line
@@ -65,6 +65,15 @@ static inline void write_maar_pair(unsigned idx, phys_addr_t lower, 
	back_to_back_c0_hazard();

}



/**

 * maar_init() - initialise MAARs

 *

 * Performs initialisation of MAARs for the current CPU, making use of the

 * platforms implementation of platform_maar_init where necessary and

 * duplicating the setup it provides on secondary CPUs.

 */

extern void maar_init(void);



/**

 * struct maar_config - MAAR configuration data

 * @lower:	The lowest address that the MAAR pair will affect. Must be