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Commit 086de575 authored by Steve Wise's avatar Steve Wise Committed by Doug Ledford
Browse files

cxgb4: advertise support for FR_NSMR_TPTE_WR



Query firmware for the FW_PARAMS_PARAM_DEV_RI_FR_NSMR_TPTE_WR parameter.
If it exists and is 1, then advertise support for FR_NSMR_TPTE_WR to
the ULDs.

Signed-off-by: default avatarSteve Wise <swise@opengridcomputing.com>
Signed-off-by: default avatarDoug Ledford <dledford@redhat.com>
parent b6bc1c73
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+1 −0
Original line number Diff line number Diff line
@@ -349,6 +349,7 @@ struct adapter_params {

	unsigned int max_ordird_qp;       /* Max read depth per RDMA QP */
	unsigned int max_ird_adapter;     /* Max read depth per adapter */
	bool fr_nsmr_tpte_wr_support;	  /* FW support for FR_NSMR_TPTE_WR */
};

/* State needed to monitor the forward progress of SGE Ingress DMA activities
+7 −0
Original line number Diff line number Diff line
@@ -2517,6 +2517,7 @@ static void uld_attach(struct adapter *adap, unsigned int uld)
	lli.max_ird_adapter = adap->params.max_ird_adapter;
	lli.ulptx_memwrite_dsgl = adap->params.ulptx_memwrite_dsgl;
	lli.nodeid = dev_to_node(adap->pdev_dev);
	lli.fr_nsmr_tpte_wr_support = adap->params.fr_nsmr_tpte_wr_support;

	handle = ulds[uld].add(&lli);
	if (IS_ERR(handle)) {
@@ -4061,6 +4062,12 @@ static int adap_init0(struct adapter *adap)
		adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
	}

	/* See if FW supports FW_RI_FR_NSMR_TPTE_WR work request */
	params[0] = FW_PARAM_DEV(RI_FR_NSMR_TPTE_WR);
	ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
			      1, params, val);
	adap->params.fr_nsmr_tpte_wr_support = (ret == 0 && val[0] != 0);

	/*
	 * Get device capabilities so we can determine what resources we need
	 * to manage.
+1 −0
Original line number Diff line number Diff line
@@ -280,6 +280,7 @@ struct cxgb4_lld_info {
	unsigned int iscsi_llimit;	     /* chip's iscsi region llimit */
	void **iscsi_ppm;		     /* iscsi page pod manager */
	int nodeid;			     /* device numa node id */
	bool fr_nsmr_tpte_wr_support;	     /* FW supports FR_NSMR_TPTE_WR */
};

struct cxgb4_uld_info {
+1 −0
Original line number Diff line number Diff line
@@ -1120,6 +1120,7 @@ enum fw_params_param_dev {
	FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER = 0x14, /* max supported adap IRD */
	FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,
	FW_PARAMS_PARAM_DEV_FWCACHE = 0x18,
	FW_PARAMS_PARAM_DEV_RI_FR_NSMR_TPTE_WR	= 0x1C,
};

/*