Merge tag 'pinctrl-v4.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Broadcom Cygnus GPIO/PINCONF Controller

Required properties:

- compatible:

    Must be "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or

    "brcm,cygnus-crmu-gpio"

- reg:

    Define the base and range of the I/O address space that contains the Cygnus

GPIO/PINCONF controller registers

- #gpio-cells:

    Must be two. The first cell is the GPIO pin number (within the

controller's pin space) and the second cell is used for the following:

    bit[0]: polarity (0 for active high and 1 for active low)

- gpio-controller:

    Specifies that the node is a GPIO controller

Optional properties:

- interrupts:

    Interrupt ID

- interrupt-controller:

    Specifies that the node is an interrupt controller

- pinmux:

    Specifies the phandle to the IOMUX device, where pins can be individually

muxed to GPIO

Supported generic PINCONF properties in child nodes:

- pins:

    The list of pins (within the controller's own pin space) that properties

in the node apply to. Pin names are "gpio-<pin>"

- bias-disable:

    Disable pin bias

- bias-pull-up:

    Enable internal pull up resistor

- bias-pull-down:

    Enable internal pull down resistor

- drive-strength:

    Valid drive strength values include 2, 4, 6, 8, 10, 12, 14, 16 (mA)

Example:

	gpio_ccm: gpio@1800a000 {

		compatible = "brcm,cygnus-ccm-gpio";

		reg = <0x1800a000 0x50>,

		      <0x0301d164 0x20>;

		#gpio-cells = <2>;

		gpio-controller;

		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-controller;

		touch_pins: touch_pins {

			pwr: pwr {

				pins = "gpio-0";

				drive-strength = <16>;

			};

			event: event {

				pins = "gpio-1";

				bias-pull-up;

			};

		};

	};

	gpio_asiu: gpio@180a5000 {

		compatible = "brcm,cygnus-asiu-gpio";

		reg = <0x180a5000 0x668>;

		#gpio-cells = <2>;

		gpio-controller;

		interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-controller;

	};

	/*

	 * Touchscreen that uses the CCM GPIO 0 and 1

	 */

	tsc {

		...

		...

		gpio-pwr = <&gpio_ccm 0 0>;

		gpio-event = <&gpio_ccm 1 0>;

	};

	/* Bluetooth that uses the ASIU GPIO 5, with polarity inverted */

	bluetooth {

		...

		...

		bcm,rfkill-bank-sel = <&gpio_asiu 5 1>

	}

Broadcom Cygnus IOMUX Controller

The Cygnus IOMUX controller supports group based mux configuration. In

addition, certain pins can be muxed to GPIO function individually.

Required properties:

- compatible:

    Must be "brcm,cygnus-pinmux"

- reg:

    Define the base and range of the I/O address space that contains the Cygnus

IOMUX registers

Properties in subnodes:

- function:

    The mux function to select

- groups:

    The list of groups to select with a given function

For more details, refer to

Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt

For example:

	pinmux: pinmux@0x0301d0c8 {

		compatible = "brcm,cygnus-pinmux";

		reg = <0x0301d0c8 0x1b0>;

		pinctrl-names = "default";

		pinctrl-0 = <&i2s0_default>;

		i2s0_default: i2s0_default {

			mux {

				function = "i2s0";

				groups = "i2s0_0_grp", "i2s0_1_grp";

			};

		};

	};

List of supported functions and groups in Cygnus:

"i2s0": "i2s0_0_grp", "i2s0_1_grp"

"i2s1": "i2s1_0_grp", "i2s1_1_grp"

"i2s2": "i2s2_0_grp", "i2s2_1_grp", "i2s2_2_grp", "i2s2_3_grp", "i2s2_4_grp"

"spdif": "spdif_grp"

"pwm0": "pwm0_grp"

"pwm1": "pwm1_grp"

"pwm2": "pwm2_grp"

"pwm3": "pwm3_grp"

"pwm4": "pwm4_grp"

"pwm5": "pwm5_grp"

"key": "key0_grp", "key1_grp", "key2_grp", "key3_grp", "key4_grp", "key5_grp",

"key6_grp", "key7_grp", "key8_grp", "key9_grp", "key10_grp", "key11_grp",

"key12_grp", "key13_grp", "key14_grp", "key15_grp"

"audio_dte": "audio_dte0_grp", "audio_dte1_grp", "audio_dte2_grp", "audio_dte3_grp"

"smart_card0": "smart_card0_grp", "smart_card0_fcb_grp"

"smart_card1": "smart_card1_grp", "smart_card1_fcb_grp"

"spi0": "spi0_grp"

"spi1": "spi1_grp"

"spi2": "spi2_grp"

"spi3": "spi3_grp"

"spi4": "spi4_0_grp", "spi4_1_grp"

"spi5": "spi5_grp"

"sw_led0": "sw_led0_0_grp", "sw_led0_1_grp"

"sw_led1": "sw_led1_grp"

"sw_led2": "sw_led2_0_grp", "sw_led2_1_grp"

"d1w": "d1w_grp"

"lcd": "lcd_grp"

"sram": "sram_0_grp", "sram_1_grp"

"uart0": "uart0_grp"

"uart1": "uart1_grp", "uart1_dte_grp"

"uart2": "uart2_grp"

"uart3": "uart3_grp"

"uart4": "uart4_grp"

"qspi": "qspi_0_grp", "qspi_1_grp"

"nand": "nand_grp"

"sdio0": "sdio0_grp", "sdio0_cd_grp", "sdio0_mmc_grp"

"sdio1": "sdio1_data_0_grp", "sdio1_data_1_grp", "sdio1_cd_grp",

"sdio1_led_grp", "sdio1_mmc_grp"

"can0": "can0_grp"

"can1": "can1_grp"

"cam": "cam_led_grp", "cam_0_grp", "cam_1_grp"

"bsc1": "bsc1_grp"

"pcie_clkreq": "pcie_clkreq_grp"

"usb0_oc": "usb0_oc_grp"

"usb1_oc": "usb1_oc_grp"

"usb2_oc": "usb2_oc_grp"

* Marvell Armada 39x SoC pinctrl driver for mpp

Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding

part and usage.

Required properties:

- compatible: "marvell,88f6920-pinctrl", "marvell,88f6928-pinctrl"

  depending on the specific variant of the SoC being used.

- reg: register specifier of MPP registers

Available mpp pins/groups and functions:

Note: brackets (x) are not part of the mpp name for marvell,function and given

only for more detailed description in this document.

name    pins    functions

================================================================================

mpp0	0	gpio, ua0(rxd)

mpp1	1	gpio, ua0(txd)

mpp2	2	gpio, i2c0(sck)

mpp3	3	gpio, i2c0(sda)

mpp4	4	gpio, ua1(txd), ua0(rts), smi(mdc)

mpp5	5	gpio, ua1(rxd), ua0(cts), smi(mdio)

mpp6	6	gpio, dev(cs3), xsmi(mdio)

mpp7	7	gpio, dev(ad9), xsmi(mdc)

mpp8	8	gpio, dev(ad10), ptp(trig)

mpp9	9	gpio, dev(ad11), ptp(clk)

mpp10	10	gpio, dev(ad12), ptp(event)

mpp11	11	gpio, dev(ad13), led(clk)

mpp12	12	gpio, pcie0(rstout), dev(ad14), led(stb)

mpp13	13	gpio, dev(ad15), led(data)

mpp14	14	gpio, m(vtt), dev(wen1), ua1(txd)

mpp15	15	gpio, pcie0(rstout), spi0(mosi), i2c1(sck)

mpp16	16	gpio, m(decc), spi0(miso), i2c1(sda)

mpp17	17	gpio, ua1(rxd), spi0(sck), smi(mdio)

mpp18	18	gpio, ua1(txd), spi0(cs0), i2c2(sck)

mpp19	19	gpio, sata1(present) [1], ua0(cts), ua1(rxd), i2c2(sda)

mpp20	20	gpio, sata0(present) [1], ua0(rts), ua1(txd), smi(mdc)

mpp21	21	gpio, spi0(cs1), sata0(present) [1], sd(cmd), dev(bootcs), ge(rxd0)

mpp22	22	gpio, spi0(mosi), dev(ad0)

mpp23	23	gpio, spi0(sck), dev(ad2)

mpp24	24	gpio, spi0(miso), ua0(cts), ua1(rxd), sd(d4), dev(readyn)

mpp25	25	gpio, spi0(cs0), ua0(rts), ua1(txd), sd(d5), dev(cs0)

mpp26	26	gpio, spi0(cs2), i2c1(sck), sd(d6), dev(cs1)

mpp27	27	gpio, spi0(cs3), i2c1(sda), sd(d7), dev(cs2), ge(txclkout)

mpp28	28	gpio, sd(clk), dev(ad5), ge(txd0)

mpp29	29	gpio, dev(ale0), ge(txd1)

mpp30	30	gpio, dev(oen), ge(txd2)

mpp31	31	gpio, dev(ale1), ge(txd3)

mpp32	32	gpio, dev(wen0), ge(txctl)

mpp33	33	gpio, m(decc), dev(ad3)

mpp34	34	gpio, dev(ad1)

mpp35	35	gpio, ref(clk), dev(a1)

mpp36	36	gpio, dev(a0)

mpp37	37	gpio, sd(d3), dev(ad8), ge(rxclk)

mpp38	38	gpio, ref(clk), sd(d0), dev(ad4), ge(rxd1)

mpp39	39	gpio, i2c1(sck), ua0(cts), sd(d1), dev(a2), ge(rxd2)

mpp40	40	gpio, i2c1(sda), ua0(rts), sd(d2), dev(ad6), ge(rxd3)

mpp41	41	gpio, ua1(rxd), ua0(cts), spi1(cs3), dev(burstn), nd(rbn0), ge(rxctl)

mpp42	42	gpio, ua1(txd), ua0(rts), dev(ad7)

mpp43	43	gpio, pcie0(clkreq), m(vtt), m(decc), spi1(cs2), dev(clkout), nd(rbn1)

mpp44	44	gpio, sata0(present) [1], sata1(present) [1], led(clk)

mpp45	45	gpio, ref(clk), pcie0(rstout), ua1(rxd)

mpp46	46	gpio, ref(clk), pcie0(rstout), ua1(txd), led(stb)

mpp47	47	gpio, sata0(present) [1], sata1(present) [1], led(data)

mpp48	48	gpio, sata0(present) [1], m(vtt), tdm(pclk) [1], audio(mclk) [1], sd(d4), pcie0(clkreq), ua1(txd)

mpp49	49	gpio, tdm(fsync) [1], audio(lrclk) [1], sd(d5), ua2(rxd)

mpp50	50	gpio, pcie0(rstout), tdm(drx) [1], audio(extclk) [1], sd(cmd), ua2(rxd)

mpp51	51	gpio, tdm(dtx) [1], audio(sdo) [1], m(decc), ua2(txd)

mpp52	52	gpio, pcie0(rstout), tdm(intn) [1], audio(sdi) [1], sd(d6), i2c3(sck)

mpp53	53	gpio, sata1(present) [1], sata0(present) [1], tdm(rstn) [1], audio(bclk) [1], sd(d7), i2c3(sda)

mpp54	54	gpio, sata0(present) [1], sata1(present) [1], pcie0(rstout), sd(d3), ua3(txd)

mpp55	55	gpio, ua1(cts), spi1(cs1), sd(d0), ua1(rxd), ua3(rxd)

mpp56	56	gpio, ua1(rts), m(decc), spi1(mosi), ua1(txd)

mpp57	57	gpio, spi1(sck), sd(clk), ua1(txd)

mpp58	58	gpio, i2c1(sck), pcie2(clkreq), spi1(miso), sd(d1), ua1(rxd)

mpp59	59	gpio, pcie0(rstout), i2c1(sda), spi1(cs0), sd(d2)

[1]: only available on 88F6928

== Amlogic Meson pinmux controller ==

Required properties for the root node:

 - compatible: "amlogic,meson8-pinctrl"

 - compatible: "amlogic,meson8-pinctrl" or "amlogic,meson8b-pinctrl"

 - reg: address and size of registers controlling irq functionality

=== GPIO sub-nodes ===

NVIDIA Tegra210 pinmux controller

Required properties:

- compatible: "nvidia,tegra210-pinmux"

- reg: Should contain a list of base address and size pairs for:

  - first entry: The APB_MISC_GP_*_PADCTRL registers (pad control)

  - second entry: The PINMUX_AUX_* registers (pinmux)

Please refer to pinctrl-bindings.txt in this directory for details of the

common pinctrl bindings used by client devices, including the meaning of the

phrase "pin configuration node".

Tegra's pin configuration nodes act as a container for an arbitrary number of

subnodes. Each of these subnodes represents some desired configuration for a

pin, a group, or a list of pins or groups. This configuration can include the

mux function to select on those pin(s)/group(s), and various pin configuration

parameters, such as pull-up, tristate, drive strength, etc.

The name of each subnode is not important; all subnodes should be enumerated

and processed purely based on their content.

Each subnode only affects those parameters that are explicitly listed. In

other words, a subnode that lists a mux function but no pin configuration

parameters implies no information about any pin configuration parameters.

Similarly, a pin subnode that describes a pullup parameter implies no

information about e.g. the mux function or tristate parameter. For this

reason, even seemingly boolean values are actually tristates in this binding:

unspecified, off, or on. Unspecified is represented as an absent property,

and off/on are represented as integer values 0 and 1.

See the TRM to determine which properties and values apply to each pin/group.

Macro values for property values are defined in

include/dt-binding/pinctrl/pinctrl-tegra.h.

Required subnode-properties:

- nvidia,pins : An array of strings. Each string contains the name of a pin or

    group. Valid values for these names are listed below.

Optional subnode-properties:

- nvidia,function: A string containing the name of the function to mux to the

    pin or group.

- nvidia,pull: Integer, representing the pull-down/up to apply to the pin.

    0: none, 1: down, 2: up.

- nvidia,tristate: Integer.

    0: drive, 1: tristate.

- nvidia,enable-input: Integer. Enable the pin's input path.

    enable :TEGRA_PIN_ENABLE0 and

    disable or output only: TEGRA_PIN_DISABLE.

- nvidia,open-drain: Integer.

    enable: TEGRA_PIN_ENABLE.

    disable: TEGRA_PIN_DISABLE.

- nvidia,lock: Integer. Lock the pin configuration against further changes

    until reset.

    enable: TEGRA_PIN_ENABLE.

    disable: TEGRA_PIN_DISABLE.

- nvidia,io-hv: Integer. Select high-voltage receivers.

    normal: TEGRA_PIN_DISABLE

    high: TEGRA_PIN_ENABLE

- nvidia,high-speed-mode: Integer. Enable high speed mode the pins.

    normal: TEGRA_PIN_DISABLE

    high: TEGRA_PIN_ENABLE

- nvidia,schmitt: Integer. Enables Schmitt Trigger on the input.

    normal: TEGRA_PIN_DISABLE

    high: TEGRA_PIN_ENABLE

- nvidia,drive-type: Integer. Valid range 0...3.

- nvidia,pull-down-strength: Integer. Controls drive strength. 0 is weakest.

    The range of valid values depends on the pingroup. See "CAL_DRVDN" in the

    Tegra TRM.

- nvidia,pull-up-strength: Integer. Controls drive strength. 0 is weakest.

    The range of valid values depends on the pingroup. See "CAL_DRVUP" in the

    Tegra TRM.

- nvidia,slew-rate-rising: Integer. Controls rising signal slew rate. 0 is

    fastest. The range of valid values depends on the pingroup. See

    "DRVDN_SLWR" in the Tegra TRM.

- nvidia,slew-rate-falling: Integer. Controls falling signal slew rate. 0 is

    fastest. The range of valid values depends on the pingroup. See

    "DRVUP_SLWF" in the Tegra TRM.

Valid values for pin and group names (nvidia,pin) are:

  Mux groups:

    These correspond to Tegra PINMUX_AUX_* (pinmux) registers. Any property

    that exists in those registers may be set for the following pin names.

    In Tegra210, many pins also have a dedicated APB_MISC_GP_*_PADCTRL

    register. Where that is true, and property that exists in that register

    may also be set on the following pin names.

    als_prox_int_px3, ap_ready_pv5, ap_wake_bt_ph3, ap_wake_nfc_ph7,

    aud_mclk_pbb0, batt_bcl, bt_rst_ph4, bt_wake_ap_ph5, button_home_py1,

    button_power_on_px5, button_slide_sw_py0, button_vol_down_px7,

    button_vol_up_px6, cam1_mclk_ps0, cam1_pwdn_ps7, cam1_strobe_pt1,

    cam2_mclk_ps1, cam2_pwdn_pt0, cam_af_en_ps5, cam_flash_en_ps6,

    cam_i2c_scl_ps2, cam_i2c_sda_ps3, cam_rst_ps4cam_rst_ps4, clk_32k_in,

    clk_32k_out_py5, clk_req, core_pwr_req, cpu_pwr_req, dap1_din_pb1,

    dap1_dout_pb2, dap1_fs_pb0, dap1_sclk_pb3, dap2_din_paa2, dap2_dout_paa3,

    dap2_fs_paa0, dap2_sclk_paa1, dap4_din_pj5, dap4_dout_pj6, dap4_fs_pj4,

    dap4_sclk_pj7, dmic1_clk_pe0, dmic1_dat_pe1, dmic2_clk_pe2, dmic2_dat_pe3,

    dmic3_clk_pe4, dmic3_dat_pe5, dp_hpd0_pcc6, dvfs_clk_pbb2, dvfs_pwm_pbb1,

    gen1_i2c_scl_pj1, gen1_i2c_sda_pj0, gen2_i2c_scl_pj2, gen2_i2c_sda_pj3,

    gen3_i2c_scl_pf0, gen3_i2c_sda_pf1, gpio_x1_aud_pbb3, gpio_x3_aud_pbb4,

    gps_en_pi2, gps_rst_pi3, hdmi_cec_pcc0, hdmi_int_dp_hpd_pcc1, jtag_rtck,

    lcd_bl_en_pv1, lcd_bl_pwm_pv0, lcd_gpio1_pv3, lcd_gpio2_pv4, lcd_rst_pv2,

    lcd_te_py2, modem_wake_ap_px0, motion_int_px2, nfc_en_pi0, nfc_int_pi1,

    pa6, pcc7, pe6, pe7, pex_l0_clkreq_n_pa1, pex_l0_rst_n_pa0,

    pex_l1_clkreq_n_pa4, pex_l1_rst_n_pa3, pex_wake_n_pa2, ph6, pk0, pk1, pk2,

    pk3, pk4, pk5, pk6, pk7, pl0, pl1, pwr_i2c_scl_py3, pwr_i2c_sda_py4,

    pwr_int_n, pz0, pz1, pz2, pz3, pz4, pz5, qspi_cs_n_pee1, qspi_io0_pee2,

    qspi_io1_pee3, qspi_io2_pee4, qspi_io3_pee5, qspi_sck_pee0,

    sata_led_active_pa5, sdmmc1_clk_pm0, sdmmc1_cmd_pm1, sdmmc1_dat0_pm5,

    sdmmc1_dat1_pm4, sdmmc1_dat2_pm3, sdmmc1_dat3_pm2, sdmmc3_clk_pp0,

    sdmmc3_cmd_pp1, sdmmc3_dat0_pp5, sdmmc3_dat1_pp4, sdmmc3_dat2_pp3,

    sdmmc3_dat3_pp2, shutdown, spdif_in_pcc3, spdif_out_pcc2, spi1_cs0_pc3,

    spi1_cs1_pc4, spi1_miso_pc1, spi1_mosi_pc0, spi1_sck_pc2, spi2_cs0_pb7,

    spi2_cs1_pdd0, spi2_miso_pb5, spi2_mosi_pb4, spi2_sck_pb6, spi4_cs0_pc6,

    spi4_miso_pd0, spi4_mosi_pc7, spi4_sck_pc5, temp_alert_px4, touch_clk_pv7,

    touch_int_px1, touch_rst_pv6, uart1_cts_pu3, uart1_rts_pu2, uart1_rx_pu1,

    uart1_tx_pu0, uart2_cts_pg3, uart2_rts_pg2, uart2_rx_pg1, uart2_tx_pg0,

    uart3_cts_pd4, uart3_rts_pd3, uart3_rx_pd2, uart3_tx_pd1, uart4_cts_pi7,

    uart4_rts_pi6, uart4_rx_pi5, uart4_tx_pi4, usb_vbus_en0_pcc4,

    usb_vbus_en1_pcc5, wifi_en_ph0, wifi_rst_ph1, wifi_wake_ap_ph2

  Drive groups:

    These correspond to the Tegra APB_MISC_GP_*_PADCTRL (pad control)

    registers. Note that where one of these registers controls a single pin

    for which a PINMUX_AUX_* exists, see the list above for the pin name to

    use when configuring the pinmux.

    pa6, pcc7, pe6, pe7, ph6, pk0, pk1, pk2, pk3, pk4, pk5, pk6, pk7, pl0, pl1,

    pz0, pz1, pz2, pz3, pz4, pz5, sdmmc1, sdmmc2, sdmmc3, sdmmc4

Valid values for nvidia,functions are:

    aud, bcl, blink, ccla, cec, cldvfs, clk, core, cpu, displaya, displayb,

    dmic1, dmic2, dmic3, dp, dtv, extperiph3, i2c1, i2c2, i2c3, i2cpmu, i2cvi,

    i2s1, i2s2, i2s3, i2s4a, i2s4b, i2s5a, i2s5b, iqc0, iqc1, jtag, pe, pe0,

    pe1, pmi, pwm0, pwm1, pwm2, pwm3, qspi, rsvd0, rsvd1, rsvd2, rsvd3, sata,

    sdmmc1, sdmmc3, shutdown, soc, sor0, sor1, spdif, spi1, spi2, spi3, spi4,

    sys, touch, uart, uarta, uartb, uartc, uartd, usb, vgp1, vgp2, vgp3, vgp4,

    vgp5, vgp6, vimclk, vimclk2

Example:

	pinmux: pinmux@70000800 {

		compatible = "nvidia,tegra210-pinmux";

		reg = <0x0 0x700008d4 0x0 0x2a8>, /* Pad control registers */

		      <0x0 0x70003000 0x0 0x1000>; /* Mux registers */

		pinctrl-names = "boot";

		pinctrl-0 = <&state_boot>;

		state_boot: pinmux {

			gen1_i2c_scl_pj1 {

				nvidia,pins = "gen1_i2c_scl_pj1",

				nvidia,function = "i2c1";

				nvidia,pull = <TEGRA_PIN_PULL_NONE>;

				nvidia,tristate = <TEGRA_PIN_DISABLE>;

				nvidia,enable-input = <TEGRA_PIN_ENABLE>;

				nvidia,open-drain = <TEGRA_PIN_ENABLE>;

				nvidia,io-hv = <TEGRA_PIN_ENABLE>;

			};

		};

	};

};