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Commit 0761ff2a authored by Geert Uytterhoeven's avatar Geert Uytterhoeven Committed by Simon Horman
Browse files

ARM: dts: r8a7794: Add SYSC PM Domains 



Add a device node for the System Controller.
Hook up the Cortex-A7 CPU cores and the Cortex-A7 L2 cache/SCU to their
respective PM Domains.

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: default avatarLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent a7ede1ab

arch/arm/boot/dts/r8a7794.dtsi

+10 −0
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ 
#include <dt-bindings/clock/r8a7794-clock.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/interrupt-controller/irq.h>

#include <dt-bindings/power/r8a7794-sysc.h>



/ {

	compatible = "renesas,r8a7794";
@@ -42,6 +43,7 @@ 
			compatible = "arm,cortex-a7";

			reg = <0>;

			clock-frequency = <1000000000>;

			power-domains = <&sysc R8A7794_PD_CA7_CPU0>;

			next-level-cache = <&L2_CA7>;

		};
@@ -50,12 +52,14 @@ 
			compatible = "arm,cortex-a7";

			reg = <1>;

			clock-frequency = <1000000000>;

			power-domains = <&sysc R8A7794_PD_CA7_CPU1>;

			next-level-cache = <&L2_CA7>;

		};

	};



	L2_CA7: cache-controller@1 {

		compatible = "cache";

		power-domains = <&sysc R8A7794_PD_CA7_SCU>;

		cache-unified;

		cache-level = <2>;

	};
@@ -1215,6 +1219,12 @@ 
		};

	};



	sysc: system-controller@e6180000 {

		compatible = "renesas,r8a7794-sysc";

		reg = <0 0xe6180000 0 0x0200>;

		#power-domain-cells = <1>;

	};



	ipmmu_sy0: mmu@e6280000 {

		compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";

		reg = <0 0xe6280000 0 0x1000>;