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Commit 0753f56e authored by Sanchayan Maity's avatar Sanchayan Maity Committed by Shawn Guo
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clk: clk-vf610: Add clock for Vybrid OCOTP controller 



Add clock support for Vybrid On-Chip One Time Programmable
(OCOTP) controller.

While the OCOTP block does not require explicit clock gating,
for programming the OCOTP timing register the clock rate of
ipg clock is required for timing calculations related to fuse
and shadow register read sequence. We explicitly specify the
ipg clock for OCOTP as a result.

Signed-off-by: default avatarSanchayan Maity <maitysanchayan@gmail.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 8efaf5ed

drivers/clk/imx/clk-vf610.c

+1 −0
Original line number Diff line number Diff line
@@ -387,6 +387,7 @@ static void __init vf610_clocks_init(struct device_node *ccm_node) 


	clk[VF610_CLK_SNVS] = imx_clk_gate2("snvs-rtc", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(7));

	clk[VF610_CLK_DAP] = imx_clk_gate("dap", "platform_bus", CCM_CCSR, 24);

	clk[VF610_CLK_OCOTP] = imx_clk_gate("ocotp", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(5));



	imx_check_clocks(clk, ARRAY_SIZE(clk));

include/dt-bindings/clock/vf610-clock.h

+2 −1
Original line number Diff line number Diff line
@@ -194,6 +194,7 @@ 
#define VF610_PLL7_BYPASS		181

#define VF610_CLK_SNVS			182

#define VF610_CLK_DAP			183

#define VF610_CLK_END			184

#define VF610_CLK_OCOTP         184

#define VF610_CLK_END			185



#endif /* __DT_BINDINGS_CLOCK_VF610_H */