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Commit 074b5e1a authored by Chris Wilson's avatar Chris Wilson Committed by Daniel Vetter
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drm/i915: Do not read non-existent DPLL registers on PCH hardware 



We only execute intel_decrease_pllclock for pre-PCH hardware, typically
gen4 mobiles. However, in the variable declaration we did read from the
non-PCH DPLL register, quite naughty and detected by SandyBridge.

Reported-and-tested-by: default avatarAndrey Rahmatullin <wrar@wrar.name>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=49025


Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-Off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 69964ea4

drivers/gpu/drm/i915/intel_display.c

+5 −4
Original line number Diff line number Diff line
@@ -7072,9 +7072,6 @@ static void intel_decrease_pllclock(struct drm_crtc *crtc) 
	struct drm_device *dev = crtc->dev;

	drm_i915_private_t *dev_priv = dev->dev_private;

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	int pipe = intel_crtc->pipe;

	int dpll_reg = DPLL(pipe);

	int dpll = I915_READ(dpll_reg);



	if (HAS_PCH_SPLIT(dev))

		return;
@@ -7087,10 +7084,15 @@ static void intel_decrease_pllclock(struct drm_crtc *crtc) 
	 * the manual case.

	 */

	if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {

		int pipe = intel_crtc->pipe;

		int dpll_reg = DPLL(pipe);

		u32 dpll;



		DRM_DEBUG_DRIVER("downclocking LVDS\n");



		assert_panel_unlocked(dev_priv, pipe);



		dpll = I915_READ(dpll_reg);

		dpll |= DISPLAY_RATE_SELECT_FPA1;

		I915_WRITE(dpll_reg, dpll);

		intel_wait_for_vblank(dev, pipe);
@@ -7098,7 +7100,6 @@ static void intel_decrease_pllclock(struct drm_crtc *crtc) 
		if (!(dpll & DISPLAY_RATE_SELECT_FPA1))

			DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");

	}



}



/**