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Commit 06e668ac authored by Mika Kuoppala's avatar Mika Kuoppala Committed by Mika Kuoppala
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drm/i915: Apply broader WaRsDisableCoarsePowerGating for guc also 



commit 344df980 ("drm/i915/skl: Disable coarse power gating up until F0")
failed to take into account that the same workaround is used in guc
when forcewake is sampled.

Wrap the condition check inside a macro and use it in both places
to fix the guc side scope.

Cc: Dave Gordon <david.s.gordon@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Reviewed-by: default avatarSagar Arun Kamble <sagar.a.kamble@intel.com>
Signed-off-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1450286318-6854-1-git-send-email-mika.kuoppala@intel.com
parent 7447a2b2

drivers/gpu/drm/i915/i915_drv.h

+5 −0
Original line number Diff line number Diff line
@@ -2576,6 +2576,11 @@ struct drm_i915_cmd_table { 


/* Early gen2 have a totally busted CS tlb and require pinned batches. */

#define HAS_BROKEN_CS_TLB(dev)		(IS_I830(dev) || IS_845G(dev))



/* WaRsDisableCoarsePowerGating:skl,bxt */

#define NEEDS_WaRsDisableCoarsePowerGating(dev) (IS_BXT_REVID(dev, 0, BXT_REVID_A1) || \

						 ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && \

						  IS_SKL_REVID(dev, 0, SKL_REVID_F0)))

/*

 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts

 * even when in MSI mode. This results in spurious interrupt warnings if the

drivers/gpu/drm/i915/i915_guc_submission.c

+2 −4
Original line number Diff line number Diff line
@@ -158,10 +158,8 @@ static int host2guc_sample_forcewake(struct intel_guc *guc, 


	data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE;

	/* WaRsDisableCoarsePowerGating:skl,bxt */

	if (!intel_enable_rc6(dev_priv->dev) ||

	    IS_BXT_REVID(dev, 0, BXT_REVID_A1) ||

	    (IS_SKL_GT3(dev) && IS_SKL_REVID(dev, 0, SKL_REVID_E0)) ||

	    (IS_SKL_GT4(dev) && IS_SKL_REVID(dev, 0, SKL_REVID_E0)))

	if (!intel_enable_rc6(dev) ||

	    NEEDS_WaRsDisableCoarsePowerGating(dev))

		data[1] = 0;

	else

		/* bit 0 and 1 are for Render and Media domain separately */

drivers/gpu/drm/i915/intel_pm.c

+1 −3
Original line number Diff line number Diff line
@@ -4713,9 +4713,7 @@ static void gen9_enable_rc6(struct drm_device *dev) 
	 * 3b: Enable Coarse Power Gating only when RC6 is enabled.

	 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.

	 */

	if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) ||

	    ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) &&

	     IS_SKL_REVID(dev, 0, SKL_REVID_F0)))

	if (NEEDS_WaRsDisableCoarsePowerGating(dev))

		I915_WRITE(GEN9_PG_ENABLE, 0);

	else

		I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?