Commit 064b4330 authored Jun 25, 2011 by Carolyn Wyborny Committed by Jeff Kirsher Jul 11, 2011

igb: Fix lack of flush after register write and before delay



Register writes followed by a delay are required to have a flush
before the delay in order to commit the values to the register.  Without
the flush, the code following the delay may not function correctly.

Reported-by: Tong Ho <tong.ho@ericsson.com>
Reported-by: Guenter Roeck <guenter.roeck@ericsson.com>
Signed-off-by: Carolyn Wyborny <carolyn.wyborny@intel.com>
Tested-by: Aaron Brown <aaron.f.brown@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>

parent d84e0bd7

drivers/net/igb/e1000_82575.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -1735,6 +1735,7 @@ static s32 igb_reset_hw_82580(struct e1000_hw *hw)
		ctrl \|= E1000_CTRL_RST;

		wr32(E1000_CTRL, ctrl);
		wrfl();

		/* Add delay to insure DEV_RST has time to complete */
		if (global_device_reset)