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Commit 05e21cc4 authored by Ben Widawsky's avatar Ben Widawsky Committed by Daniel Vetter
Browse files

drm/i915: Define some of the eLLC magic 



The EDRAM present register isn't really defined in the docs. It just
says check to see if it's set to 1. So I haven't defined the 1 value not
knowing what it actually means.

Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 0d8ff15e

drivers/gpu/drm/i915/i915_gem.c

+2 −2
Original line number Diff line number Diff line
@@ -4147,8 +4147,8 @@ i915_gem_init_hw(struct drm_device *dev) 
	if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())

		return -EIO;



	if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1))

		I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);

	if (IS_HASWELL(dev) && (I915_READ(HSW_EDRAM_PRESENT) == 1))

		I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));



	if (HAS_PCH_NOP(dev)) {

		u32 temp = I915_READ(GEN7_MSG_CTL);

drivers/gpu/drm/i915/i915_reg.h

+4 −0
Original line number Diff line number Diff line
@@ -4472,6 +4472,10 @@ 
#define  GT_FIFO_FREE_ENTRIES			0x120008

#define    GT_FIFO_NUM_RESERVED_ENTRIES		20



#define  HSW_IDICR				0x9008

#define    IDIHASHMSK(x)			(((x) & 0x3f) << 16)

#define  HSW_EDRAM_PRESENT			0x120010



#define GEN6_UCGCTL1				0x9400

# define GEN6_BLBUNIT_CLOCK_GATE_DISABLE		(1 << 5)

# define GEN6_CSUNIT_CLOCK_GATE_DISABLE			(1 << 7)