Merge git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6 (05249755) · Commits · e / devices / android_kernel_teracube_2e

Documentation/devicetree/bindings/crypto/fsl-sec4.txt

0 → 100644

+397 −0

Original line number	Original line	Diff line number	Diff line
			=====================================================================
			SEC 4 Device Tree Binding
			Copyright (C) 2008-2011 Freescale Semiconductor Inc.

			CONTENTS
			-Overview
			-SEC 4 Node
			-Job Ring Node
			-Run Time Integrity Check (RTIC) Node
			-Run Time Integrity Check (RTIC) Memory Node
			-Secure Non-Volatile Storage (SNVS) Node
			-Full Example

			NOTE: the SEC 4 is also known as Freescale's Cryptographic Accelerator
			Accelerator and Assurance Module (CAAM).

			=====================================================================
			Overview

			DESCRIPTION

			SEC 4 h/w can process requests from 2 types of sources.
			1. DPAA Queue Interface (HW interface between Queue Manager & SEC 4).
			2. Job Rings (HW interface between cores & SEC 4 registers).

			High Speed Data Path Configuration:

			HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts
			such as the P4080. The number of simultaneous dequeues the QI can make is
			equal to the number of Descriptor Controller (DECO) engines in a particular
			SEC version. E.g., the SEC 4.0 in the P4080 has 5 DECOs and can thus
			dequeue from 5 subportals simultaneously.

			Job Ring Data Path Configuration:

			Each JR is located on a separate 4k page, they may (or may not) be made visible
			in the memory partition devoted to a particular core. The P4080 has 4 JRs, so
			up to 4 JRs can be configured; and all 4 JRs process requests in parallel.

			=====================================================================
			SEC 4 Node

			Description

			Node defines the base address of the SEC 4 block.
			This block specifies the address range of all global
			configuration registers for the SEC 4 block. It
			also receives interrupts from the Run Time Integrity Check
			(RTIC) function within the SEC 4 block.

			PROPERTIES

			- compatible
			Usage: required
			Value type: <string>
			Definition: Must include "fsl,sec-v4.0"

			- #address-cells
			Usage: required
			Value type: <u32>
			Definition: A standard property. Defines the number of cells
			for representing physical addresses in child nodes.

			- #size-cells
			Usage: required
			Value type: <u32>
			Definition: A standard property. Defines the number of cells
			for representing the size of physical addresses in
			child nodes.

			- reg
			Usage: required
			Value type: <prop-encoded-array>
			Definition: A standard property. Specifies the physical
			address and length of the SEC4 configuration registers.
			registers

			- ranges
			Usage: required
			Value type: <prop-encoded-array>
			Definition: A standard property. Specifies the physical address
			range of the SEC 4.0 register space (-SNVS not included). A
			triplet that includes the child address, parent address, &
			length.

			- interrupts
			Usage: required
			Value type: <prop_encoded-array>
			Definition: Specifies the interrupts generated by this
			device. The value of the interrupts property
			consists of one interrupt specifier. The format
			of the specifier is defined by the binding document
			describing the node's interrupt parent.

			- interrupt-parent
			Usage: (required if interrupt property is defined)
			Value type: <phandle>
			Definition: A single <phandle> value that points
			to the interrupt parent to which the child domain
			is being mapped.

			Note: All other standard properties (see the ePAPR) are allowed
			but are optional.


			EXAMPLE
			crypto@300000 {
			compatible = "fsl,sec-v4.0";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x300000 0x10000>;
			ranges = <0 0x300000 0x10000>;
			interrupt-parent = <&mpic>;
			interrupts = <92 2>;
			};

			=====================================================================
			Job Ring (JR) Node

			Child of the crypto node defines data processing interface to SEC 4
			across the peripheral bus for purposes of processing
			cryptographic descriptors. The specified address
			range can be made visible to one (or more) cores.
			The interrupt defined for this node is controlled within
			the address range of this node.

			- compatible
			Usage: required
			Value type: <string>
			Definition: Must include "fsl,sec-v4.0-job-ring"

			- reg
			Usage: required
			Value type: <prop-encoded-array>
			Definition: Specifies a two JR parameters: an offset from
			the parent physical address and the length the JR registers.

			- fsl,liodn
			Usage: optional-but-recommended
			Value type: <prop-encoded-array>
			Definition:
			Specifies the LIODN to be used in conjunction with
			the ppid-to-liodn table that specifies the PPID to LIODN mapping.
			Needed if the PAMU is used. Value is a 12 bit value
			where value is a LIODN ID for this JR. This property is
			normally set by boot firmware.

			- interrupts
			Usage: required
			Value type: <prop_encoded-array>
			Definition: Specifies the interrupts generated by this
			device. The value of the interrupts property
			consists of one interrupt specifier. The format
			of the specifier is defined by the binding document
			describing the node's interrupt parent.

			- interrupt-parent
			Usage: (required if interrupt property is defined)
			Value type: <phandle>
			Definition: A single <phandle> value that points
			to the interrupt parent to which the child domain
			is being mapped.

			EXAMPLE
			jr@1000 {
			compatible = "fsl,sec-v4.0-job-ring";
			reg = <0x1000 0x1000>;
			fsl,liodn = <0x081>;
			interrupt-parent = <&mpic>;
			interrupts = <88 2>;
			};


			=====================================================================
			Run Time Integrity Check (RTIC) Node

			Child node of the crypto node. Defines a register space that
			contains up to 5 sets of addresses and their lengths (sizes) that
			will be checked at run time. After an initial hash result is
			calculated, these addresses are checked by HW to monitor any
			change. If any memory is modified, a Security Violation is
			triggered (see SNVS definition).


			- compatible
			Usage: required
			Value type: <string>
			Definition: Must include "fsl,sec-v4.0-rtic".

			- #address-cells
			Usage: required
			Value type: <u32>
			Definition: A standard property. Defines the number of cells
			for representing physical addresses in child nodes. Must
			have a value of 1.

			- #size-cells
			Usage: required
			Value type: <u32>
			Definition: A standard property. Defines the number of cells
			for representing the size of physical addresses in
			child nodes. Must have a value of 1.

			- reg
			Usage: required
			Value type: <prop-encoded-array>
			Definition: A standard property. Specifies a two parameters:
			an offset from the parent physical address and the length
			the SEC4 registers.

			- ranges
			Usage: required
			Value type: <prop-encoded-array>
			Definition: A standard property. Specifies the physical address
			range of the SEC 4 register space (-SNVS not included). A
			triplet that includes the child address, parent address, &
			length.

			EXAMPLE
			rtic@6000 {
			compatible = "fsl,sec-v4.0-rtic";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x6000 0x100>;
			ranges = <0x0 0x6100 0xe00>;
			};

			=====================================================================
			Run Time Integrity Check (RTIC) Memory Node
			A child node that defines individual RTIC memory regions that are used to
			perform run-time integrity check of memory areas that should not modified.
			The node defines a register that contains the memory address &
			length (combined) and a second register that contains the hash result
			in big endian format.

			- compatible
			Usage: required
			Value type: <string>
			Definition: Must include "fsl,sec-v4.0-rtic-memory".

			- reg
			Usage: required
			Value type: <prop-encoded-array>
			Definition: A standard property. Specifies two parameters:
			an offset from the parent physical address and the length:

			1. The location of the RTIC memory address & length registers.
			2. The location RTIC hash result.

			- fsl,rtic-region
			Usage: optional-but-recommended
			Value type: <prop-encoded-array>
			Definition:
			Specifies the HW address (36 bit address) for this region
			followed by the length of the HW partition to be checked;
			the address is represented as a 64 bit quantity followed
			by a 32 bit length.

			- fsl,liodn
			Usage: optional-but-recommended
			Value type: <prop-encoded-array>
			Definition:
			Specifies the LIODN to be used in conjunction with
			the ppid-to-liodn table that specifies the PPID to LIODN
			mapping. Needed if the PAMU is used. Value is a 12 bit value
			where value is a LIODN ID for this RTIC memory region. This
			property is normally set by boot firmware.

			EXAMPLE
			rtic-a@0 {
			compatible = "fsl,sec-v4.0-rtic-memory";
			reg = <0x00 0x20 0x100 0x80>;
			fsl,liodn = <0x03c>;
			fsl,rtic-region = <0x12345678 0x12345678 0x12345678>;
			};

			=====================================================================
			Secure Non-Volatile Storage (SNVS) Node

			Node defines address range and the associated
			interrupt for the SNVS function. This function
			monitors security state information & reports
			security violations.

			- compatible
			Usage: required
			Value type: <string>
			Definition: Must include "fsl,sec-v4.0-mon".

			- reg
			Usage: required
			Value type: <prop-encoded-array>
			Definition: A standard property. Specifies the physical
			address and length of the SEC4 configuration
			registers.

			- interrupts
			Usage: required
			Value type: <prop_encoded-array>
			Definition: Specifies the interrupts generated by this
			device. The value of the interrupts property
			consists of one interrupt specifier. The format
			of the specifier is defined by the binding document
			describing the node's interrupt parent.

			- interrupt-parent
			Usage: (required if interrupt property is defined)
			Value type: <phandle>
			Definition: A single <phandle> value that points
			to the interrupt parent to which the child domain
			is being mapped.

			EXAMPLE
			sec_mon@314000 {
			compatible = "fsl,sec-v4.0-mon";
			reg = <0x314000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <93 2>;
			};

			=====================================================================
			FULL EXAMPLE

			crypto: crypto@300000 {
			compatible = "fsl,sec-v4.0";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x300000 0x10000>;
			ranges = <0 0x300000 0x10000>;
			interrupt-parent = <&mpic>;
			interrupts = <92 2>;

			sec_jr0: jr@1000 {
			compatible = "fsl,sec-v4.0-job-ring";
			reg = <0x1000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <88 2>;
			};

			sec_jr1: jr@2000 {
			compatible = "fsl,sec-v4.0-job-ring";
			reg = <0x2000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <89 2>;
			};

			sec_jr2: jr@3000 {
			compatible = "fsl,sec-v4.0-job-ring";
			reg = <0x3000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <90 2>;
			};

			sec_jr3: jr@4000 {
			compatible = "fsl,sec-v4.0-job-ring";
			reg = <0x4000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <91 2>;
			};

			rtic@6000 {
			compatible = "fsl,sec-v4.0-rtic";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x6000 0x100>;
			ranges = <0x0 0x6100 0xe00>;

			rtic_a: rtic-a@0 {
			compatible = "fsl,sec-v4.0-rtic-memory";
			reg = <0x00 0x20 0x100 0x80>;
			};

			rtic_b: rtic-b@20 {
			compatible = "fsl,sec-v4.0-rtic-memory";
			reg = <0x20 0x20 0x200 0x80>;
			};

			rtic_c: rtic-c@40 {
			compatible = "fsl,sec-v4.0-rtic-memory";
			reg = <0x40 0x20 0x300 0x80>;
			};

			rtic_d: rtic-d@60 {
			compatible = "fsl,sec-v4.0-rtic-memory";
			reg = <0x60 0x20 0x500 0x80>;
			};
			};
			};

			sec_mon: sec_mon@314000 {
			compatible = "fsl,sec-v4.0-mon";
			reg = <0x314000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <93 2>;
			};

			=====================================================================

arch/powerpc/boot/dts/p4080ds.dts

+85 −1

Original line number	Original line	Diff line number	Diff line
	/*		/*
	* P4080DS Device Tree Source		* P4080DS Device Tree Source
	*		*
	* Copyright 2009 Freescale Semiconductor Inc.		* Copyright 2009-2011 Freescale Semiconductor Inc.
	*		*
	* This program is free software; you can redistribute it and/or modify it		* This program is free software; you can redistribute it and/or modify it
	* under the terms of the GNU General Public License as published by the		* under the terms of the GNU General Public License as published by the
	@@ -33,6 +33,17 @@
	dma1 = &dma1;		dma1 = &dma1;
	sdhc = &sdhc;		sdhc = &sdhc;

			crypto = &crypto;
			sec_jr0 = &sec_jr0;
			sec_jr1 = &sec_jr1;
			sec_jr2 = &sec_jr2;
			sec_jr3 = &sec_jr3;
			rtic_a = &rtic_a;
			rtic_b = &rtic_b;
			rtic_c = &rtic_c;
			rtic_d = &rtic_d;
			sec_mon = &sec_mon;

	rio0 = &rapidio0;		rio0 = &rapidio0;
	};		};

	@@ -410,6 +421,79 @@
	dr_mode = "host";		dr_mode = "host";
	phy_type = "ulpi";		phy_type = "ulpi";
	};		};

			crypto: crypto@300000 {
			compatible = "fsl,sec-v4.0";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x300000 0x10000>;
			ranges = <0 0x300000 0x10000>;
			interrupt-parent = <&mpic>;
			interrupts = <92 2>;

			sec_jr0: jr@1000 {
			compatible = "fsl,sec-v4.0-job-ring";
			reg = <0x1000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <88 2>;
			};

			sec_jr1: jr@2000 {
			compatible = "fsl,sec-v4.0-job-ring";
			reg = <0x2000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <89 2>;
			};

			sec_jr2: jr@3000 {
			compatible = "fsl,sec-v4.0-job-ring";
			reg = <0x3000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <90 2>;
			};

			sec_jr3: jr@4000 {
			compatible = "fsl,sec-v4.0-job-ring";
			reg = <0x4000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <91 2>;
			};

			rtic@6000 {
			compatible = "fsl,sec-v4.0-rtic";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x6000 0x100>;
			ranges = <0x0 0x6100 0xe00>;

			rtic_a: rtic-a@0 {
			compatible = "fsl,sec-v4.0-rtic-memory";
			reg = <0x00 0x20 0x100 0x80>;
			};

			rtic_b: rtic-b@20 {
			compatible = "fsl,sec-v4.0-rtic-memory";
			reg = <0x20 0x20 0x200 0x80>;
			};

			rtic_c: rtic-c@40 {
			compatible = "fsl,sec-v4.0-rtic-memory";
			reg = <0x40 0x20 0x300 0x80>;
			};

			rtic_d: rtic-d@60 {
			compatible = "fsl,sec-v4.0-rtic-memory";
			reg = <0x60 0x20 0x500 0x80>;
			};
			};
			};

			sec_mon: sec_mon@314000 {
			compatible = "fsl,sec-v4.0-mon";
			reg = <0x314000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <93 2>;
			};
	};		};

	rapidio0: rapidio@ffe0c0000 {		rapidio0: rapidio@ffe0c0000 {

arch/s390/crypto/Makefile

+1 −0

Original line number	Original line	Diff line number	Diff line
	@@ -8,3 +8,4 @@ obj-$(CONFIG_CRYPTO_SHA512_S390) += sha512_s390.o sha_common.o
	obj-$(CONFIG_CRYPTO_DES_S390) += des_s390.o		obj-$(CONFIG_CRYPTO_DES_S390) += des_s390.o
	obj-$(CONFIG_CRYPTO_AES_S390) += aes_s390.o		obj-$(CONFIG_CRYPTO_AES_S390) += aes_s390.o
	obj-$(CONFIG_S390_PRNG) += prng.o		obj-$(CONFIG_S390_PRNG) += prng.o
			obj-$(CONFIG_CRYPTO_GHASH_S390) += ghash_s390.o

arch/s390/crypto/aes_s390.c

+379 −4

File changed.

Preview size limit exceeded, changes collapsed.

arch/s390/crypto/crypt_s390.h

+108 −4

Original line number	Original line	Diff line number	Diff line
	@@ -24,13 +24,18 @@
	#define CRYPT_S390_PRIORITY 300		#define CRYPT_S390_PRIORITY 300
	#define CRYPT_S390_COMPOSITE_PRIORITY 400		#define CRYPT_S390_COMPOSITE_PRIORITY 400

			#define CRYPT_S390_MSA 0x1
			#define CRYPT_S390_MSA3 0x2
			#define CRYPT_S390_MSA4 0x4

	/* s390 cryptographic operations */		/* s390 cryptographic operations */
	enum crypt_s390_operations {		enum crypt_s390_operations {
	CRYPT_S390_KM = 0x0100,		CRYPT_S390_KM = 0x0100,
	CRYPT_S390_KMC = 0x0200,		CRYPT_S390_KMC = 0x0200,
	CRYPT_S390_KIMD = 0x0300,		CRYPT_S390_KIMD = 0x0300,
	CRYPT_S390_KLMD = 0x0400,		CRYPT_S390_KLMD = 0x0400,
	CRYPT_S390_KMAC = 0x0500		CRYPT_S390_KMAC = 0x0500,
			CRYPT_S390_KMCTR = 0x0600
	};		};

	/*		/*
	@@ -51,6 +56,10 @@ enum crypt_s390_km_func {
	KM_AES_192_DECRYPT = CRYPT_S390_KM \| 0x13 \| 0x80,		KM_AES_192_DECRYPT = CRYPT_S390_KM \| 0x13 \| 0x80,
	KM_AES_256_ENCRYPT = CRYPT_S390_KM \| 0x14,		KM_AES_256_ENCRYPT = CRYPT_S390_KM \| 0x14,
	KM_AES_256_DECRYPT = CRYPT_S390_KM \| 0x14 \| 0x80,		KM_AES_256_DECRYPT = CRYPT_S390_KM \| 0x14 \| 0x80,
			KM_XTS_128_ENCRYPT = CRYPT_S390_KM \| 0x32,
			KM_XTS_128_DECRYPT = CRYPT_S390_KM \| 0x32 \| 0x80,
			KM_XTS_256_ENCRYPT = CRYPT_S390_KM \| 0x34,
			KM_XTS_256_DECRYPT = CRYPT_S390_KM \| 0x34 \| 0x80,
	};		};

	/*		/*
	@@ -74,6 +83,26 @@ enum crypt_s390_kmc_func {
	KMC_PRNG = CRYPT_S390_KMC \| 0x43,		KMC_PRNG = CRYPT_S390_KMC \| 0x43,
	};		};

			/*
			* function codes for KMCTR (CIPHER MESSAGE WITH COUNTER)
			* instruction
			*/
			enum crypt_s390_kmctr_func {
			KMCTR_QUERY = CRYPT_S390_KMCTR \| 0x0,
			KMCTR_DEA_ENCRYPT = CRYPT_S390_KMCTR \| 0x1,
			KMCTR_DEA_DECRYPT = CRYPT_S390_KMCTR \| 0x1 \| 0x80,
			KMCTR_TDEA_128_ENCRYPT = CRYPT_S390_KMCTR \| 0x2,
			KMCTR_TDEA_128_DECRYPT = CRYPT_S390_KMCTR \| 0x2 \| 0x80,
			KMCTR_TDEA_192_ENCRYPT = CRYPT_S390_KMCTR \| 0x3,
			KMCTR_TDEA_192_DECRYPT = CRYPT_S390_KMCTR \| 0x3 \| 0x80,
			KMCTR_AES_128_ENCRYPT = CRYPT_S390_KMCTR \| 0x12,
			KMCTR_AES_128_DECRYPT = CRYPT_S390_KMCTR \| 0x12 \| 0x80,
			KMCTR_AES_192_ENCRYPT = CRYPT_S390_KMCTR \| 0x13,
			KMCTR_AES_192_DECRYPT = CRYPT_S390_KMCTR \| 0x13 \| 0x80,
			KMCTR_AES_256_ENCRYPT = CRYPT_S390_KMCTR \| 0x14,
			KMCTR_AES_256_DECRYPT = CRYPT_S390_KMCTR \| 0x14 \| 0x80,
			};

	/*		/*
	* function codes for KIMD (COMPUTE INTERMEDIATE MESSAGE DIGEST)		* function codes for KIMD (COMPUTE INTERMEDIATE MESSAGE DIGEST)
	* instruction		* instruction
	@@ -83,6 +112,7 @@ enum crypt_s390_kimd_func {
	KIMD_SHA_1 = CRYPT_S390_KIMD \| 1,		KIMD_SHA_1 = CRYPT_S390_KIMD \| 1,
	KIMD_SHA_256 = CRYPT_S390_KIMD \| 2,		KIMD_SHA_256 = CRYPT_S390_KIMD \| 2,
	KIMD_SHA_512 = CRYPT_S390_KIMD \| 3,		KIMD_SHA_512 = CRYPT_S390_KIMD \| 3,
			KIMD_GHASH = CRYPT_S390_KIMD \| 65,
	};		};

	/*		/*
	@@ -283,6 +313,45 @@ static inline int crypt_s390_kmac(long func, void *param,
	return (func & CRYPT_S390_FUNC_MASK) ? src_len - __src_len : __src_len;		return (func & CRYPT_S390_FUNC_MASK) ? src_len - __src_len : __src_len;
	}		}

			/**
			* crypt_s390_kmctr:
			* @func: the function code passed to KMCTR; see crypt_s390_kmctr_func
			* @param: address of parameter block; see POP for details on each func
			* @dest: address of destination memory area
			* @src: address of source memory area
			* @src_len: length of src operand in bytes
			* @counter: address of counter value
			*
			* Executes the KMCTR (CIPHER MESSAGE WITH COUNTER) operation of the CPU.
			*
			* Returns -1 for failure, 0 for the query func, number of processed
			* bytes for encryption/decryption funcs
			*/
			static inline int crypt_s390_kmctr(long func, void param, u8 dest,
			const u8 src, long src_len, u8 counter)
			{
			register long __func asm("0") = func & CRYPT_S390_FUNC_MASK;
			register void *__param asm("1") = param;
			register const u8 *__src asm("2") = src;
			register long __src_len asm("3") = src_len;
			register u8 *__dest asm("4") = dest;
			register u8 *__ctr asm("6") = counter;
			int ret = -1;

			asm volatile(
			"0: .insn rrf,0xb92d0000,%3,%1,%4,0 \n" /* KMCTR opcode */
			"1: brc 1,0b \n" /* handle partial completion */
			" la %0,0\n"
			"2:\n"
			EX_TABLE(0b,2b) EX_TABLE(1b,2b)
			: "+d" (ret), "+a" (__src), "+d" (__src_len), "+a" (__dest),
			"+a" (__ctr)
			: "d" (__func), "a" (__param) : "cc", "memory");
			if (ret < 0)
			return ret;
			return (func & CRYPT_S390_FUNC_MASK) ? src_len - __src_len : __src_len;
			}

	/**		/**
	* crypt_s390_func_available:		* crypt_s390_func_available:
	* @func: the function code of the specific function; 0 if op in general		* @func: the function code of the specific function; 0 if op in general
	@@ -291,13 +360,17 @@ static inline int crypt_s390_kmac(long func, void *param,
	*		*
	* Returns 1 if func available; 0 if func or op in general not available		* Returns 1 if func available; 0 if func or op in general not available
	*/		*/
	static inline int crypt_s390_func_available(int func)		static inline int crypt_s390_func_available(int func,
			unsigned int facility_mask)
	{		{
	unsigned char status[16];		unsigned char status[16];
	int ret;		int ret;

	/* check if CPACF facility (bit 17) is available */		if (facility_mask & CRYPT_S390_MSA && !test_facility(17))
	if (!test_facility(17))		return 0;
			if (facility_mask & CRYPT_S390_MSA3 && !test_facility(76))
			return 0;
			if (facility_mask & CRYPT_S390_MSA4 && !test_facility(77))
	return 0;		return 0;

	switch (func & CRYPT_S390_OP_MASK) {		switch (func & CRYPT_S390_OP_MASK) {
	@@ -316,6 +389,10 @@ static inline int crypt_s390_func_available(int func)
	case CRYPT_S390_KMAC:		case CRYPT_S390_KMAC:
	ret = crypt_s390_kmac(KMAC_QUERY, &status, NULL, 0);		ret = crypt_s390_kmac(KMAC_QUERY, &status, NULL, 0);
	break;		break;
			case CRYPT_S390_KMCTR:
			ret = crypt_s390_kmctr(KMCTR_QUERY, &status, NULL, NULL, 0,
			NULL);
			break;
	default:		default:
	return 0;		return 0;
	}		}
	@@ -326,4 +403,31 @@ static inline int crypt_s390_func_available(int func)
	return (status[func >> 3] & (0x80 >> (func & 7))) != 0;		return (status[func >> 3] & (0x80 >> (func & 7))) != 0;
	}		}

			/**
			* crypt_s390_pcc:
			* @func: the function code passed to KM; see crypt_s390_km_func
			* @param: address of parameter block; see POP for details on each func
			*
			* Executes the PCC (PERFORM CRYPTOGRAPHIC COMPUTATION) operation of the CPU.
			*
			* Returns -1 for failure, 0 for success.
			*/
			static inline int crypt_s390_pcc(long func, void *param)
			{
			register long __func asm("0") = func & 0x7f; /* encrypt or decrypt */
			register void *__param asm("1") = param;
			int ret = -1;

			asm volatile(
			"0: .insn rre,0xb92c0000,0,0 \n" /* PCC opcode */
			"1: brc 1,0b \n" /* handle partial completion */
			" la %0,0\n"
			"2:\n"
			EX_TABLE(0b,2b) EX_TABLE(1b,2b)
			: "+d" (ret)
			: "d" (__func), "a" (__param) : "cc", "memory");
			return ret;
			}


	#endif /* _CRYPTO_ARCH_S390_CRYPT_S390_H */		#endif /* _CRYPTO_ARCH_S390_CRYPT_S390_H */