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Commit 0499bdeb authored by Tony Lindgren's avatar Tony Lindgren
Browse files

ARM: OMAP: DMA: Remove __REG access 



Remove __REG access in DMA code, use dma_read/write instead:

- dynamically set the omap_dma_base based on the omap type
- omap_read/write becomes dma_read/write
- dma channel registers are read with dma_ch_read/write

Cc: David Brownell <david-b@pacbell.net>
Cc: linux-usb@vger.kernel.org
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent 4d96372e

arch/arm/plat-omap/dma.c

+324 −179

File changed.

Preview size limit exceeded, changes collapsed.

drivers/usb/gadget/omap_udc.c

+6 −36
Original line number Diff line number Diff line
@@ -491,32 +491,6 @@ static int read_fifo(struct omap_ep *ep, struct omap_req *req) 


/*-------------------------------------------------------------------------*/



static inline dma_addr_t dma_csac(unsigned lch)

{

	dma_addr_t	csac;



	/* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is

	 * read before the DMA controller finished disabling the channel.

	 */

	csac = OMAP_DMA_CSAC_REG(lch);

	if (csac == 0)

		csac = OMAP_DMA_CSAC_REG(lch);

	return csac;

}



static inline dma_addr_t dma_cdac(unsigned lch)

{

	dma_addr_t	cdac;



	/* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is

	 * read before the DMA controller finished disabling the channel.

	 */

	cdac = OMAP_DMA_CDAC_REG(lch);

	if (cdac == 0)

		cdac = OMAP_DMA_CDAC_REG(lch);

	return cdac;

}



static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)

{

	dma_addr_t	end;
@@ -527,7 +501,7 @@ static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start) 
	if (cpu_is_omap15xx())

		return 0;



	end = dma_csac(ep->lch);

	end = omap_get_dma_src_pos(ep->lch);

	if (end == ep->dma_counter)

		return 0;
@@ -537,15 +511,11 @@ static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start) 
	return end - start;

}



#define DMA_DEST_LAST(x) (cpu_is_omap15xx() \

		? OMAP_DMA_CSAC_REG(x) /* really: CPC */ \

		: dma_cdac(x))



static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start)

{

	dma_addr_t	end;



	end = DMA_DEST_LAST(ep->lch);

	end = omap_get_dma_dst_pos(ep->lch);

	if (end == ep->dma_counter)

		return 0;
@@ -596,7 +566,7 @@ static void next_in_dma(struct omap_ep *ep, struct omap_req *req) 
		0, 0);



	omap_start_dma(ep->lch);

	ep->dma_counter = dma_csac(ep->lch);

	ep->dma_counter = omap_get_dma_src_pos(ep->lch);

	UDC_DMA_IRQ_EN_REG |= UDC_TX_DONE_IE(ep->dma_channel);

	UDC_TXDMA_REG(ep->dma_channel) = UDC_TXN_START | txdma_ctrl;

	req->dma_bytes = length;
@@ -654,7 +624,7 @@ static void next_out_dma(struct omap_ep *ep, struct omap_req *req) 
	omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF,

		OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,

		0, 0);

	ep->dma_counter = DMA_DEST_LAST(ep->lch);

	ep->dma_counter = omap_get_dma_dst_pos(ep->lch);



	UDC_RXDMA_REG(ep->dma_channel) = UDC_RXN_STOP | (packets - 1);

	UDC_DMA_IRQ_EN_REG |= UDC_RX_EOT_IE(ep->dma_channel);
@@ -834,7 +804,7 @@ static void dma_channel_claim(struct omap_ep *ep, unsigned channel) 


		/* channel type P: hw synch (fifo) */

		if (cpu_class_is_omap1() && !cpu_is_omap15xx())

			OMAP1_DMA_LCH_CTRL_REG(ep->lch) = 2;

			omap_set_dma_channel_mode(ep->lch, OMAP_DMA_LCH_P);

	}



just_restart:
@@ -881,7 +851,7 @@ static void dma_channel_release(struct omap_ep *ep) 
	else

		req = NULL;



	active = ((1 << 7) & OMAP_DMA_CCR_REG(ep->lch)) != 0;

	active = omap_get_dma_active_status(ep->lch);



	DBG("%s release %s %cxdma%d %p\n", ep->ep.name,

			active ? "active" : "idle",

include/asm-arm/arch-omap/dma.h

+120 −90
Original line number Diff line number Diff line
@@ -22,107 +22,128 @@ 
#define __ASM_ARCH_DMA_H



/* Hardware registers for omap1 */

#define OMAP_DMA_BASE			(0xfffed800)

#define OMAP_DMA_GCR			(OMAP_DMA_BASE + 0x400)

#define OMAP_DMA_GSCR			(OMAP_DMA_BASE + 0x404)

#define OMAP_DMA_GRST			(OMAP_DMA_BASE + 0x408)

#define OMAP_DMA_HW_ID			(OMAP_DMA_BASE + 0x442)

#define OMAP_DMA_PCH2_ID		(OMAP_DMA_BASE + 0x444)

#define OMAP_DMA_PCH0_ID		(OMAP_DMA_BASE + 0x446)

#define OMAP_DMA_PCH1_ID		(OMAP_DMA_BASE + 0x448)

#define OMAP_DMA_PCHG_ID		(OMAP_DMA_BASE + 0x44a)

#define OMAP_DMA_PCHD_ID		(OMAP_DMA_BASE + 0x44c)

#define OMAP_DMA_CAPS_0_U		(OMAP_DMA_BASE + 0x44e)

#define OMAP_DMA_CAPS_0_L		(OMAP_DMA_BASE + 0x450)

#define OMAP_DMA_CAPS_1_U		(OMAP_DMA_BASE + 0x452)

#define OMAP_DMA_CAPS_1_L		(OMAP_DMA_BASE + 0x454)

#define OMAP_DMA_CAPS_2			(OMAP_DMA_BASE + 0x456)

#define OMAP_DMA_CAPS_3			(OMAP_DMA_BASE + 0x458)

#define OMAP_DMA_CAPS_4			(OMAP_DMA_BASE + 0x45a)

#define OMAP_DMA_PCH2_SR		(OMAP_DMA_BASE + 0x460)

#define OMAP_DMA_PCH0_SR		(OMAP_DMA_BASE + 0x480)

#define OMAP_DMA_PCH1_SR		(OMAP_DMA_BASE + 0x482)

#define OMAP_DMA_PCHD_SR		(OMAP_DMA_BASE + 0x4c0)



/* Hardware registers for omap2 */

#if defined(CONFIG_ARCH_OMAP3)

#define OMAP_DMA4_BASE			(L4_34XX_BASE + 0x56000)

#else	/* CONFIG_ARCH_OMAP2 */

#define OMAP_DMA4_BASE			(L4_24XX_BASE + 0x56000)

#endif



#define OMAP_DMA4_REVISION		(OMAP_DMA4_BASE + 0x00)

#define OMAP_DMA4_GCR_REG		(OMAP_DMA4_BASE + 0x78)

#define OMAP_DMA4_IRQSTATUS_L0		(OMAP_DMA4_BASE + 0x08)

#define OMAP_DMA4_IRQSTATUS_L1		(OMAP_DMA4_BASE + 0x0c)

#define OMAP_DMA4_IRQSTATUS_L2		(OMAP_DMA4_BASE + 0x10)

#define OMAP_DMA4_IRQSTATUS_L3		(OMAP_DMA4_BASE + 0x14)

#define OMAP_DMA4_IRQENABLE_L0		(OMAP_DMA4_BASE + 0x18)

#define OMAP_DMA4_IRQENABLE_L1		(OMAP_DMA4_BASE + 0x1c)

#define OMAP_DMA4_IRQENABLE_L2		(OMAP_DMA4_BASE + 0x20)

#define OMAP_DMA4_IRQENABLE_L3		(OMAP_DMA4_BASE + 0x24)

#define OMAP_DMA4_SYSSTATUS		(OMAP_DMA4_BASE + 0x28)

#define OMAP_DMA4_OCP_SYSCONFIG		(OMAP_DMA4_BASE + 0x2c)

#define OMAP_DMA4_CAPS_0		(OMAP_DMA4_BASE + 0x64)

#define OMAP_DMA4_CAPS_2		(OMAP_DMA4_BASE + 0x6c)

#define OMAP_DMA4_CAPS_3		(OMAP_DMA4_BASE + 0x70)

#define OMAP_DMA4_CAPS_4		(OMAP_DMA4_BASE + 0x74)

#define OMAP1_DMA_BASE			(0xfffed800)



#define OMAP1_DMA_GCR			0x400

#define OMAP1_DMA_GSCR			0x404

#define OMAP1_DMA_GRST			0x408

#define OMAP1_DMA_HW_ID			0x442

#define OMAP1_DMA_PCH2_ID		0x444

#define OMAP1_DMA_PCH0_ID		0x446

#define OMAP1_DMA_PCH1_ID		0x448

#define OMAP1_DMA_PCHG_ID		0x44a

#define OMAP1_DMA_PCHD_ID		0x44c

#define OMAP1_DMA_CAPS_0_U		0x44e

#define OMAP1_DMA_CAPS_0_L		0x450

#define OMAP1_DMA_CAPS_1_U		0x452

#define OMAP1_DMA_CAPS_1_L		0x454

#define OMAP1_DMA_CAPS_2		0x456

#define OMAP1_DMA_CAPS_3		0x458

#define OMAP1_DMA_CAPS_4		0x45a

#define OMAP1_DMA_PCH2_SR		0x460

#define OMAP1_DMA_PCH0_SR		0x480

#define OMAP1_DMA_PCH1_SR		0x482

#define OMAP1_DMA_PCHD_SR		0x4c0



/* Hardware registers for omap2 and omap3 */

#define OMAP24XX_DMA4_BASE		(L4_24XX_BASE + 0x56000)

#define OMAP34XX_DMA4_BASE		(L4_34XX_BASE + 0x56000)



#define OMAP_DMA4_REVISION		0x00

#define OMAP_DMA4_GCR			0x78

#define OMAP_DMA4_IRQSTATUS_L0		0x08

#define OMAP_DMA4_IRQSTATUS_L1		0x0c

#define OMAP_DMA4_IRQSTATUS_L2		0x10

#define OMAP_DMA4_IRQSTATUS_L3		0x14

#define OMAP_DMA4_IRQENABLE_L0		0x18

#define OMAP_DMA4_IRQENABLE_L1		0x1c

#define OMAP_DMA4_IRQENABLE_L2		0x20

#define OMAP_DMA4_IRQENABLE_L3		0x24

#define OMAP_DMA4_SYSSTATUS		0x28

#define OMAP_DMA4_OCP_SYSCONFIG		0x2c

#define OMAP_DMA4_CAPS_0		0x64

#define OMAP_DMA4_CAPS_2		0x6c

#define OMAP_DMA4_CAPS_3		0x70

#define OMAP_DMA4_CAPS_4		0x74



#define OMAP1_LOGICAL_DMA_CH_COUNT	17

#define OMAP_DMA4_LOGICAL_DMA_CH_COUNT	32	/* REVISIT: Is this 32 + 2? */



#ifdef CONFIG_ARCH_OMAP1



/* Common channel specific registers for omap1 */

#define OMAP_DMA_CSDP_REG(n)		__REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x00)

#define OMAP_DMA_CCR_REG(n)		__REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x02)

#define OMAP_DMA_CICR_REG(n)		__REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x04)

#define OMAP_DMA_CSR_REG(n)		__REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x06)

#define OMAP_DMA_CEN_REG(n)		__REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x10)

#define OMAP_DMA_CFN_REG(n)		__REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x12)

#define OMAP_DMA_CSFI_REG(n)		__REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x14)

#define OMAP_DMA_CSEI_REG(n)		__REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x16)

#define OMAP_DMA_CSAC_REG(n)		__REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x18)

#define OMAP_DMA_CDAC_REG(n)		__REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1a)

#define OMAP_DMA_CDEI_REG(n)		__REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1c)

#define OMAP_DMA_CDFI_REG(n)		__REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1e)

#define OMAP_DMA_CLNK_CTRL_REG(n)	__REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x28)



#else

#define OMAP1_DMA_CH_BASE(n)		(0x40 * (n) + 0x00)

#define OMAP1_DMA_CSDP(n)		(0x40 * (n) + 0x00)

#define OMAP1_DMA_CCR(n)		(0x40 * (n) + 0x02)

#define OMAP1_DMA_CICR(n)		(0x40 * (n) + 0x04)

#define OMAP1_DMA_CSR(n)		(0x40 * (n) + 0x06)

#define OMAP1_DMA_CEN(n)		(0x40 * (n) + 0x10)

#define OMAP1_DMA_CFN(n)		(0x40 * (n) + 0x12)

#define OMAP1_DMA_CSFI(n)		(0x40 * (n) + 0x14)

#define OMAP1_DMA_CSEI(n)		(0x40 * (n) + 0x16)

#define OMAP1_DMA_CPC(n)		(0x40 * (n) + 0x18)	/* 15xx only */

#define OMAP1_DMA_CSAC(n)		(0x40 * (n) + 0x18)

#define OMAP1_DMA_CDAC(n)		(0x40 * (n) + 0x1a)

#define OMAP1_DMA_CDEI(n)		(0x40 * (n) + 0x1c)

#define OMAP1_DMA_CDFI(n)		(0x40 * (n) + 0x1e)

#define OMAP1_DMA_CLNK_CTRL(n)		(0x40 * (n) + 0x28)



/* Common channel specific registers for omap2 */

#define OMAP_DMA_CCR_REG(n)		__REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x80)

#define OMAP_DMA_CLNK_CTRL_REG(n)	__REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x84)

#define OMAP_DMA_CICR_REG(n)		__REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x88)

#define OMAP_DMA_CSR_REG(n)		__REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x8c)

#define OMAP_DMA_CSDP_REG(n)		__REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x90)

#define OMAP_DMA_CEN_REG(n)		__REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x94)

#define OMAP_DMA_CFN_REG(n)		__REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x98)

#define OMAP_DMA_CSEI_REG(n)		__REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa4)

#define OMAP_DMA_CSFI_REG(n)		__REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa8)

#define OMAP_DMA_CDEI_REG(n)		__REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xac)

#define OMAP_DMA_CDFI_REG(n)		__REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb0)

#define OMAP_DMA_CSAC_REG(n)		__REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb4)

#define OMAP_DMA_CDAC_REG(n)		__REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb8)



#endif

#define OMAP_DMA4_CH_BASE(n)		(0x60 * (n) + 0x80)

#define OMAP_DMA4_CCR(n)		(0x60 * (n) + 0x80)

#define OMAP_DMA4_CLNK_CTRL(n)		(0x60 * (n) + 0x84)

#define OMAP_DMA4_CICR(n)		(0x60 * (n) + 0x88)

#define OMAP_DMA4_CSR(n)		(0x60 * (n) + 0x8c)

#define OMAP_DMA4_CSDP(n)		(0x60 * (n) + 0x90)

#define OMAP_DMA4_CEN(n)		(0x60 * (n) + 0x94)

#define OMAP_DMA4_CFN(n)		(0x60 * (n) + 0x98)

#define OMAP_DMA4_CSEI(n)		(0x60 * (n) + 0xa4)

#define OMAP_DMA4_CSFI(n)		(0x60 * (n) + 0xa8)

#define OMAP_DMA4_CDEI(n)		(0x60 * (n) + 0xac)

#define OMAP_DMA4_CDFI(n)		(0x60 * (n) + 0xb0)

#define OMAP_DMA4_CSAC(n)		(0x60 * (n) + 0xb4)

#define OMAP_DMA4_CDAC(n)		(0x60 * (n) + 0xb8)



/* Channel specific registers only on omap1 */

#define OMAP1_DMA_CSSA_L_REG(n)		__REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x08)

#define OMAP1_DMA_CSSA_U_REG(n)		__REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0a)

#define OMAP1_DMA_CDSA_L_REG(n)		__REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0c)

#define OMAP1_DMA_CDSA_U_REG(n)		__REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0e)

#define OMAP1_DMA_COLOR_L_REG(n)	__REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x20)

#define OMAP1_DMA_CCR2_REG(n)		__REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x24)

#define OMAP1_DMA_COLOR_U_REG(n)	__REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x22)

#define OMAP1_DMA_LCH_CTRL_REG(n)	__REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x2a)

#define OMAP1_DMA_CSSA_L(n)		(0x40 * (n) + 0x08)

#define OMAP1_DMA_CSSA_U(n)		(0x40 * (n) + 0x0a)

#define OMAP1_DMA_CDSA_L(n)		(0x40 * (n) + 0x0c)

#define OMAP1_DMA_CDSA_U(n)		(0x40 * (n) + 0x0e)

#define OMAP1_DMA_COLOR_L(n)		(0x40 * (n) + 0x20)

#define OMAP1_DMA_COLOR_U(n)		(0x40 * (n) + 0x22)

#define OMAP1_DMA_CCR2(n)		(0x40 * (n) + 0x24)

#define OMAP1_DMA_LCH_CTRL(n)		(0x40 * (n) + 0x2a)	/* not on 15xx */

#define OMAP1_DMA_CCEN(n)		0

#define OMAP1_DMA_CCFN(n)		0



/* Channel specific registers only on omap2 */

#define OMAP2_DMA_CSSA_REG(n)		__REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x9c)

#define OMAP2_DMA_CDSA_REG(n)		__REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa0)

#define OMAP2_DMA_CCEN_REG(n)		__REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xbc)

#define OMAP2_DMA_CCFN_REG(n)		__REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xc0)

#define OMAP2_DMA_COLOR_REG(n)		__REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xc4)

#define OMAP_DMA4_CSSA(n)		(0x60 * (n) + 0x9c)

#define OMAP_DMA4_CDSA(n)		(0x60 * (n) + 0xa0)

#define OMAP_DMA4_CCEN(n)		(0x60 * (n) + 0xbc)

#define OMAP_DMA4_CCFN(n)		(0x60 * (n) + 0xc0)

#define OMAP_DMA4_COLOR(n)		(0x60 * (n) + 0xc4)



/* Dummy defines to keep multi-omap compiles happy */

#define OMAP1_DMA_REVISION		0

#define OMAP1_DMA_IRQSTATUS_L0		0

#define OMAP1_DMA_IRQENABLE_L0		0

#define OMAP1_DMA_OCP_SYSCONFIG		0

#define OMAP_DMA4_HW_ID			0

#define OMAP_DMA4_CAPS_0_L		0

#define OMAP_DMA4_CAPS_0_U		0

#define OMAP_DMA4_CAPS_1_L		0

#define OMAP_DMA4_CAPS_1_U		0

#define OMAP_DMA4_GSCR			0

#define OMAP_DMA4_CPC(n)		0



#define OMAP_DMA4_LCH_CTRL(n)		0

#define OMAP_DMA4_COLOR_L(n)		0

#define OMAP_DMA4_COLOR_U(n)		0

#define OMAP_DMA4_CCR2(n)		0

#define OMAP1_DMA_CSSA(n)		0

#define OMAP1_DMA_CDSA(n)		0

#define OMAP_DMA4_CSSA_L(n)		0

#define OMAP_DMA4_CSSA_U(n)		0

#define OMAP_DMA4_CDSA_L(n)		0

#define OMAP_DMA4_CDSA_U(n)		0



/*----------------------------------------------------------------------------*/
@@ -369,6 +390,13 @@ enum omap_dma_write_mode { 
	OMAP_DMA_WRITE_LAST_NON_POSTED

};



enum omap_dma_channel_mode {

	OMAP_DMA_LCH_2D = 0,

	OMAP_DMA_LCH_G,

	OMAP_DMA_LCH_P,

	OMAP_DMA_LCH_PD

};



struct omap_dma_channel_params {

	int data_type;		/* data type 8,16,32 */

	int elem_count;		/* number of elements in a frame */
@@ -417,6 +445,7 @@ extern void omap_set_dma_transfer_params(int lch, int data_type, 
extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode,

				    u32 color);

extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode);

extern void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode);



extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,

				    unsigned long src_start,
@@ -447,6 +476,7 @@ extern dma_addr_t omap_get_dma_src_pos(int lch); 
extern dma_addr_t omap_get_dma_dst_pos(int lch);

extern int omap_get_dma_src_addr_counter(int lch);

extern void omap_clear_dma(int lch);

extern int omap_get_dma_active_status(int lch);

extern int omap_dma_running(void);

extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth,

				       int tparams);