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Commit 03e3905f authored by Eric Huang's avatar Eric Huang Committed by Alex Deucher
Browse files

drm/amd/powerplay: add all blocks clockgating support through SMU/powerplay 



Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarEric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent e85c7d66

drivers/gpu/drm/amd/powerplay/amd_powerplay.c

+81 −0
Original line number Diff line number Diff line
@@ -180,6 +180,87 @@ static void pp_print_status(void *handle) 
static int pp_set_clockgating_state(void *handle,

				    enum amd_clockgating_state state)

{

	struct pp_hwmgr  *hwmgr;

	uint32_t msg_id, pp_state;



	if (handle == NULL)

		return -EINVAL;



	hwmgr = ((struct pp_instance *)handle)->hwmgr;



	if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||

			hwmgr->hwmgr_func->update_clock_gatings == NULL)

			return -EINVAL;



	if (state == AMD_CG_STATE_UNGATE)

		pp_state = 0;

	else

		pp_state = PP_STATE_CG | PP_STATE_LS;



	/* Enable/disable GFX blocks clock gating through SMU */

	msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,

			PP_BLOCK_GFX_CG,

			PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,

			pp_state);

	hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);

	msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,

			PP_BLOCK_GFX_3D,

			PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,

			pp_state);

	hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);

	msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,

			PP_BLOCK_GFX_RLC,

			PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,

			pp_state);

	hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);

	msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,

			PP_BLOCK_GFX_CP,

			PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,

			pp_state);

	hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);

	msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,

			PP_BLOCK_GFX_MG,

			PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,

			pp_state);

	hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);



	/* Enable/disable System blocks clock gating through SMU */

	msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,

			PP_BLOCK_SYS_BIF,

			PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,

			pp_state);

	hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);

	msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,

			PP_BLOCK_SYS_BIF,

			PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,

			pp_state);

	hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);

	msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,

			PP_BLOCK_SYS_MC,

			PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,

			pp_state);

	hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);

	msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,

			PP_BLOCK_SYS_ROM,

			PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,

			pp_state);

	hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);

	msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,

			PP_BLOCK_SYS_DRM,

			PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,

			pp_state);

	hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);

	msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,

			PP_BLOCK_SYS_HDP,

			PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,

			pp_state);

	hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);

	msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,

			PP_BLOCK_SYS_SDMA,

			PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,

			pp_state);

	hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);



	return 0;

}

drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h

+3 −0
Original line number Diff line number Diff line
@@ -289,6 +289,9 @@ struct pp_states_info { 


#define PP_BLOCK_GFX_CG         0x01

#define PP_BLOCK_GFX_MG         0x02

#define PP_BLOCK_GFX_3D         0x04

#define PP_BLOCK_GFX_RLC        0x08

#define PP_BLOCK_GFX_CP         0x10

#define PP_BLOCK_SYS_BIF        0x01

#define PP_BLOCK_SYS_MC         0x02

#define PP_BLOCK_SYS_ROM        0x04