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Commit 03b3f4c8 authored by Thierry Reding's avatar Thierry Reding
Browse files

soc/tegra: fuse: Rename core_* to soc_* 



There's a mixture of core_* and soc_* prefixes for variables storing
information related to the VDD_CORE rail. Choose one (soc_*) and use it
more consistently.

Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 0dc5a0d8

drivers/soc/tegra/fuse/fuse-tegra.c

+4 −4
Original line number Diff line number Diff line
@@ -304,11 +304,11 @@ static int __init tegra_init_fuse(void) 


	fuse->soc->init(fuse);



	pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",

	pr_info("Tegra Revision: %s SKU: %d CPU Process: %d SoC Process: %d\n",

		tegra_revision_name[tegra_sku_info.revision],

		tegra_sku_info.sku_id, tegra_sku_info.cpu_process_id,

		tegra_sku_info.core_process_id);

	pr_debug("Tegra CPU Speedo ID %d, Soc Speedo ID %d\n",

		tegra_sku_info.soc_process_id);

	pr_debug("Tegra CPU Speedo ID %d, SoC Speedo ID %d\n",

		 tegra_sku_info.cpu_speedo_id, tegra_sku_info.soc_speedo_id);



	return 0;

drivers/soc/tegra/fuse/fuse-tegra20.c

+1 −1
Original line number Diff line number Diff line
@@ -143,7 +143,7 @@ static void __init tegra20_fuse_add_randomness(void) 
	randomness[1] = tegra_read_straps();

	randomness[2] = tegra_read_chipid();

	randomness[3] = tegra_sku_info.cpu_process_id << 16;

	randomness[3] |= tegra_sku_info.core_process_id;

	randomness[3] |= tegra_sku_info.soc_process_id;

	randomness[4] = tegra_sku_info.cpu_speedo_id << 16;

	randomness[4] |= tegra_sku_info.soc_speedo_id;

	randomness[5] = tegra_fuse_read_early(FUSE_UID_LOW);

drivers/soc/tegra/fuse/fuse-tegra30.c

+1 −1
Original line number Diff line number Diff line
@@ -78,7 +78,7 @@ static void __init tegra30_fuse_add_randomness(void) 
	randomness[1] = tegra_read_straps();

	randomness[2] = tegra_read_chipid();

	randomness[3] = tegra_sku_info.cpu_process_id << 16;

	randomness[3] |= tegra_sku_info.core_process_id;

	randomness[3] |= tegra_sku_info.soc_process_id;

	randomness[4] = tegra_sku_info.cpu_speedo_id << 16;

	randomness[4] |= tegra_sku_info.soc_speedo_id;

	randomness[5] = tegra_fuse_read_early(FUSE_VENDOR_CODE);

drivers/soc/tegra/fuse/speedo-tegra114.c

+8 −8
Original line number Diff line number Diff line
@@ -22,7 +22,7 @@ 


#include "fuse.h"



#define CORE_PROCESS_CORNERS	2

#define SOC_PROCESS_CORNERS	2

#define CPU_PROCESS_CORNERS	2



enum {
@@ -31,7 +31,7 @@ enum { 
	THRESHOLD_INDEX_COUNT,

};



static const u32 __initconst core_process_speedos[][CORE_PROCESS_CORNERS] = {

static const u32 __initconst soc_process_speedos[][SOC_PROCESS_CORNERS] = {

	{1123,     UINT_MAX},

	{0,        UINT_MAX},

};
@@ -84,27 +84,27 @@ static void __init rev_sku_to_speedo_ids(struct tegra_sku_info *sku_info, 
void __init tegra114_init_speedo_data(struct tegra_sku_info *sku_info)

{

	u32 cpu_speedo_val;

	u32 core_speedo_val;

	u32 soc_speedo_val;

	int threshold;

	int i;



	BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) !=

			THRESHOLD_INDEX_COUNT);

	BUILD_BUG_ON(ARRAY_SIZE(core_process_speedos) !=

	BUILD_BUG_ON(ARRAY_SIZE(soc_process_speedos) !=

			THRESHOLD_INDEX_COUNT);



	rev_sku_to_speedo_ids(sku_info, &threshold);



	cpu_speedo_val = tegra_fuse_read_early(0x12c) + 1024;

	core_speedo_val = tegra_fuse_read_early(0x134);

	soc_speedo_val = tegra_fuse_read_early(0x134);



	for (i = 0; i < CPU_PROCESS_CORNERS; i++)

		if (cpu_speedo_val < cpu_process_speedos[threshold][i])

			break;

	sku_info->cpu_process_id = i;



	for (i = 0; i < CORE_PROCESS_CORNERS; i++)

		if (core_speedo_val < core_process_speedos[threshold][i])

	for (i = 0; i < SOC_PROCESS_CORNERS; i++)

		if (soc_speedo_val < soc_process_speedos[threshold][i])

			break;

	sku_info->core_process_id = i;

	sku_info->soc_process_id = i;

}

drivers/soc/tegra/fuse/speedo-tegra124.c

+6 −6
Original line number Diff line number Diff line
@@ -24,7 +24,7 @@ 


#define CPU_PROCESS_CORNERS	2

#define GPU_PROCESS_CORNERS	2

#define CORE_PROCESS_CORNERS	2

#define SOC_PROCESS_CORNERS	2



#define FUSE_CPU_SPEEDO_0	0x14

#define FUSE_CPU_SPEEDO_1	0x2c
@@ -53,7 +53,7 @@ static const u32 __initconst gpu_process_speedos[][GPU_PROCESS_CORNERS] = { 
	{0,	UINT_MAX},

};



static const u32 __initconst core_process_speedos[][CORE_PROCESS_CORNERS] = {

static const u32 __initconst soc_process_speedos[][SOC_PROCESS_CORNERS] = {

	{2101,	UINT_MAX},

	{0,	UINT_MAX},

};
@@ -119,7 +119,7 @@ void __init tegra124_init_speedo_data(struct tegra_sku_info *sku_info) 
			THRESHOLD_INDEX_COUNT);

	BUILD_BUG_ON(ARRAY_SIZE(gpu_process_speedos) !=

			THRESHOLD_INDEX_COUNT);

	BUILD_BUG_ON(ARRAY_SIZE(core_process_speedos) !=

	BUILD_BUG_ON(ARRAY_SIZE(soc_process_speedos) !=

			THRESHOLD_INDEX_COUNT);



	cpu_speedo_0_value = tegra_fuse_read_early(FUSE_CPU_SPEEDO_0);
@@ -157,11 +157,11 @@ void __init tegra124_init_speedo_data(struct tegra_sku_info *sku_info) 
				break;

	sku_info->cpu_process_id = i;



	for (i = 0; i < CORE_PROCESS_CORNERS; i++)

	for (i = 0; i < SOC_PROCESS_CORNERS; i++)

		if (soc_speedo_0_value <

			core_process_speedos[threshold][i])

			soc_process_speedos[threshold][i])

			break;

	sku_info->core_process_id = i;

	sku_info->soc_process_id = i;



	pr_debug("Tegra GPU Speedo ID=%d, Speedo Value=%d\n",

		 sku_info->gpu_speedo_id, sku_info->gpu_speedo_value);