Loading arch/x86/crypto/aesni-intel_asm.S +32 −16 Original line number Diff line number Diff line Loading @@ -2681,56 +2681,68 @@ ENTRY(aesni_xts_crypt8) addq %rcx, KEYP movdqa IV, STATE1 pxor 0x00(INP), STATE1 movdqu 0x00(INP), INC pxor INC, STATE1 movdqu IV, 0x00(OUTP) _aesni_gf128mul_x_ble() movdqa IV, STATE2 pxor 0x10(INP), STATE2 movdqu 0x10(INP), INC pxor INC, STATE2 movdqu IV, 0x10(OUTP) _aesni_gf128mul_x_ble() movdqa IV, STATE3 pxor 0x20(INP), STATE3 movdqu 0x20(INP), INC pxor INC, STATE3 movdqu IV, 0x20(OUTP) _aesni_gf128mul_x_ble() movdqa IV, STATE4 pxor 0x30(INP), STATE4 movdqu 0x30(INP), INC pxor INC, STATE4 movdqu IV, 0x30(OUTP) call *%r11 pxor 0x00(OUTP), STATE1 movdqu 0x00(OUTP), INC pxor INC, STATE1 movdqu STATE1, 0x00(OUTP) _aesni_gf128mul_x_ble() movdqa IV, STATE1 pxor 0x40(INP), STATE1 movdqu 0x40(INP), INC pxor INC, STATE1 movdqu IV, 0x40(OUTP) pxor 0x10(OUTP), STATE2 movdqu 0x10(OUTP), INC pxor INC, STATE2 movdqu STATE2, 0x10(OUTP) _aesni_gf128mul_x_ble() movdqa IV, STATE2 pxor 0x50(INP), STATE2 movdqu 0x50(INP), INC pxor INC, STATE2 movdqu IV, 0x50(OUTP) pxor 0x20(OUTP), STATE3 movdqu 0x20(OUTP), INC pxor INC, STATE3 movdqu STATE3, 0x20(OUTP) _aesni_gf128mul_x_ble() movdqa IV, STATE3 pxor 0x60(INP), STATE3 movdqu 0x60(INP), INC pxor INC, STATE3 movdqu IV, 0x60(OUTP) pxor 0x30(OUTP), STATE4 movdqu 0x30(OUTP), INC pxor INC, STATE4 movdqu STATE4, 0x30(OUTP) _aesni_gf128mul_x_ble() movdqa IV, STATE4 pxor 0x70(INP), STATE4 movdqu 0x70(INP), INC pxor INC, STATE4 movdqu IV, 0x70(OUTP) _aesni_gf128mul_x_ble() Loading @@ -2738,16 +2750,20 @@ ENTRY(aesni_xts_crypt8) call *%r11 pxor 0x40(OUTP), STATE1 movdqu 0x40(OUTP), INC pxor INC, STATE1 movdqu STATE1, 0x40(OUTP) pxor 0x50(OUTP), STATE2 movdqu 0x50(OUTP), INC pxor INC, STATE2 movdqu STATE2, 0x50(OUTP) pxor 0x60(OUTP), STATE3 movdqu 0x60(OUTP), INC pxor INC, STATE3 movdqu STATE3, 0x60(OUTP) pxor 0x70(OUTP), STATE4 movdqu 0x70(OUTP), INC pxor INC, STATE4 movdqu STATE4, 0x70(OUTP) ret Loading arch/x86/crypto/sha256-avx-asm.S +1 −1 Original line number Diff line number Diff line Loading @@ -118,7 +118,7 @@ y2 = %r15d _INP_END_SIZE = 8 _INP_SIZE = 8 _XFER_SIZE = 8 _XFER_SIZE = 16 _XMM_SAVE_SIZE = 0 _INP_END = 0 Loading arch/x86/crypto/sha256-ssse3-asm.S +1 −1 Original line number Diff line number Diff line Loading @@ -111,7 +111,7 @@ y2 = %r15d _INP_END_SIZE = 8 _INP_SIZE = 8 _XFER_SIZE = 8 _XFER_SIZE = 16 _XMM_SAVE_SIZE = 0 _INP_END = 0 Loading drivers/crypto/caam/caamalg.c +2 −2 Original line number Diff line number Diff line Loading @@ -1154,7 +1154,7 @@ static struct aead_edesc *aead_edesc_alloc(struct aead_request *req, dst_nents = sg_count(req->dst, req->cryptlen, &dst_chained); sgc = dma_map_sg_chained(jrdev, req->assoc, assoc_nents ? : 1, DMA_BIDIRECTIONAL, assoc_chained); DMA_TO_DEVICE, assoc_chained); if (likely(req->src == req->dst)) { sgc = dma_map_sg_chained(jrdev, req->src, src_nents ? : 1, DMA_BIDIRECTIONAL, src_chained); Loading Loading @@ -1336,7 +1336,7 @@ static struct aead_edesc *aead_giv_edesc_alloc(struct aead_givcrypt_request dst_nents = sg_count(req->dst, req->cryptlen, &dst_chained); sgc = dma_map_sg_chained(jrdev, req->assoc, assoc_nents ? : 1, DMA_BIDIRECTIONAL, assoc_chained); DMA_TO_DEVICE, assoc_chained); if (likely(req->src == req->dst)) { sgc = dma_map_sg_chained(jrdev, req->src, src_nents ? : 1, DMA_BIDIRECTIONAL, src_chained); Loading drivers/crypto/sahara.c +1 −1 Original line number Diff line number Diff line Loading @@ -863,7 +863,7 @@ static struct of_device_id sahara_dt_ids[] = { { .compatible = "fsl,imx27-sahara" }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(platform, sahara_dt_ids); MODULE_DEVICE_TABLE(of, sahara_dt_ids); static int sahara_probe(struct platform_device *pdev) { Loading Loading
arch/x86/crypto/aesni-intel_asm.S +32 −16 Original line number Diff line number Diff line Loading @@ -2681,56 +2681,68 @@ ENTRY(aesni_xts_crypt8) addq %rcx, KEYP movdqa IV, STATE1 pxor 0x00(INP), STATE1 movdqu 0x00(INP), INC pxor INC, STATE1 movdqu IV, 0x00(OUTP) _aesni_gf128mul_x_ble() movdqa IV, STATE2 pxor 0x10(INP), STATE2 movdqu 0x10(INP), INC pxor INC, STATE2 movdqu IV, 0x10(OUTP) _aesni_gf128mul_x_ble() movdqa IV, STATE3 pxor 0x20(INP), STATE3 movdqu 0x20(INP), INC pxor INC, STATE3 movdqu IV, 0x20(OUTP) _aesni_gf128mul_x_ble() movdqa IV, STATE4 pxor 0x30(INP), STATE4 movdqu 0x30(INP), INC pxor INC, STATE4 movdqu IV, 0x30(OUTP) call *%r11 pxor 0x00(OUTP), STATE1 movdqu 0x00(OUTP), INC pxor INC, STATE1 movdqu STATE1, 0x00(OUTP) _aesni_gf128mul_x_ble() movdqa IV, STATE1 pxor 0x40(INP), STATE1 movdqu 0x40(INP), INC pxor INC, STATE1 movdqu IV, 0x40(OUTP) pxor 0x10(OUTP), STATE2 movdqu 0x10(OUTP), INC pxor INC, STATE2 movdqu STATE2, 0x10(OUTP) _aesni_gf128mul_x_ble() movdqa IV, STATE2 pxor 0x50(INP), STATE2 movdqu 0x50(INP), INC pxor INC, STATE2 movdqu IV, 0x50(OUTP) pxor 0x20(OUTP), STATE3 movdqu 0x20(OUTP), INC pxor INC, STATE3 movdqu STATE3, 0x20(OUTP) _aesni_gf128mul_x_ble() movdqa IV, STATE3 pxor 0x60(INP), STATE3 movdqu 0x60(INP), INC pxor INC, STATE3 movdqu IV, 0x60(OUTP) pxor 0x30(OUTP), STATE4 movdqu 0x30(OUTP), INC pxor INC, STATE4 movdqu STATE4, 0x30(OUTP) _aesni_gf128mul_x_ble() movdqa IV, STATE4 pxor 0x70(INP), STATE4 movdqu 0x70(INP), INC pxor INC, STATE4 movdqu IV, 0x70(OUTP) _aesni_gf128mul_x_ble() Loading @@ -2738,16 +2750,20 @@ ENTRY(aesni_xts_crypt8) call *%r11 pxor 0x40(OUTP), STATE1 movdqu 0x40(OUTP), INC pxor INC, STATE1 movdqu STATE1, 0x40(OUTP) pxor 0x50(OUTP), STATE2 movdqu 0x50(OUTP), INC pxor INC, STATE2 movdqu STATE2, 0x50(OUTP) pxor 0x60(OUTP), STATE3 movdqu 0x60(OUTP), INC pxor INC, STATE3 movdqu STATE3, 0x60(OUTP) pxor 0x70(OUTP), STATE4 movdqu 0x70(OUTP), INC pxor INC, STATE4 movdqu STATE4, 0x70(OUTP) ret Loading
arch/x86/crypto/sha256-avx-asm.S +1 −1 Original line number Diff line number Diff line Loading @@ -118,7 +118,7 @@ y2 = %r15d _INP_END_SIZE = 8 _INP_SIZE = 8 _XFER_SIZE = 8 _XFER_SIZE = 16 _XMM_SAVE_SIZE = 0 _INP_END = 0 Loading
arch/x86/crypto/sha256-ssse3-asm.S +1 −1 Original line number Diff line number Diff line Loading @@ -111,7 +111,7 @@ y2 = %r15d _INP_END_SIZE = 8 _INP_SIZE = 8 _XFER_SIZE = 8 _XFER_SIZE = 16 _XMM_SAVE_SIZE = 0 _INP_END = 0 Loading
drivers/crypto/caam/caamalg.c +2 −2 Original line number Diff line number Diff line Loading @@ -1154,7 +1154,7 @@ static struct aead_edesc *aead_edesc_alloc(struct aead_request *req, dst_nents = sg_count(req->dst, req->cryptlen, &dst_chained); sgc = dma_map_sg_chained(jrdev, req->assoc, assoc_nents ? : 1, DMA_BIDIRECTIONAL, assoc_chained); DMA_TO_DEVICE, assoc_chained); if (likely(req->src == req->dst)) { sgc = dma_map_sg_chained(jrdev, req->src, src_nents ? : 1, DMA_BIDIRECTIONAL, src_chained); Loading Loading @@ -1336,7 +1336,7 @@ static struct aead_edesc *aead_giv_edesc_alloc(struct aead_givcrypt_request dst_nents = sg_count(req->dst, req->cryptlen, &dst_chained); sgc = dma_map_sg_chained(jrdev, req->assoc, assoc_nents ? : 1, DMA_BIDIRECTIONAL, assoc_chained); DMA_TO_DEVICE, assoc_chained); if (likely(req->src == req->dst)) { sgc = dma_map_sg_chained(jrdev, req->src, src_nents ? : 1, DMA_BIDIRECTIONAL, src_chained); Loading
drivers/crypto/sahara.c +1 −1 Original line number Diff line number Diff line Loading @@ -863,7 +863,7 @@ static struct of_device_id sahara_dt_ids[] = { { .compatible = "fsl,imx27-sahara" }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(platform, sahara_dt_ids); MODULE_DEVICE_TABLE(of, sahara_dt_ids); static int sahara_probe(struct platform_device *pdev) { Loading