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Commit 021f6537 authored by Marc Zyngier's avatar Marc Zyngier Committed by Jason Cooper
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irqchip: gic-v3: Initial support for GICv3 



The Generic Interrupt Controller (version 3) offers services that are
similar to GICv2, with a number of additional features:
- Affinity routing based on the CPU MPIDR (ARE)
- System register for the CPU interfaces (SRE)
- Support for more that 8 CPUs
- Locality-specific Peripheral Interrupts (LPIs)
- Interrupt Translation Services (ITS)

This patch adds preliminary support for GICv3 with ARE and SRE,
non-secure mode only. It relies on higher exception levels to grant ARE
and SRE access.

Support for LPI and ITS will be added at a later time.

Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Reviewed-by: default avatarZi Shen Lim <zlim@broadcom.com>
Reviewed-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
Reviewed-by: default avatarTirumalesh Chalamarla <tchalamarla@cavium.com>
Reviewed-by: default avatarYun Wu <wuyun.wu@huawei.com>
Reviewed-by: default avatarZhen Lei <thunder.leizhen@huawei.com>
Tested-by: default avatarTirumalesh <Chalamarla&lt;tchalamarla@cavium.com>
Tested-by: default avatarRadha Mohan Chintakuntla <rchintakuntla@cavium.com>
Acked-by: default avatarRadha Mohan Chintakuntla <rchintakuntla@cavium.com>
Acked-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Reviewed-by: default avatarMark Rutland <mark.rutland@arm.com>
Link: https://lkml.kernel.org/r/1404140510-5382-3-git-send-email-marc.zyngier@arm.com


Signed-off-by: default avatarJason Cooper <jason@lakedaemon.net>
parent d51d0af4

arch/arm64/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ config ARM64 
	select ARM_AMBA

	select ARM_ARCH_TIMER

	select ARM_GIC

	select ARM_GIC_V3

	select BUILDTIME_EXTABLE_SORT

	select CLONE_BACKWARDS

	select COMMON_CLK

arch/arm64/kernel/head.S

+18 −0
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ 


#include <linux/linkage.h>

#include <linux/init.h>

#include <linux/irqchip/arm-gic-v3.h>



#include <asm/assembler.h>

#include <asm/ptrace.h>
@@ -296,6 +297,23 @@ CPU_LE( bic x0, x0, #(3 << 24) ) // Clear the EE and E0E bits for EL1 
	msr	cnthctl_el2, x0

	msr	cntvoff_el2, xzr		// Clear virtual offset



#ifdef CONFIG_ARM_GIC_V3

	/* GICv3 system register access */

	mrs	x0, id_aa64pfr0_el1

	ubfx	x0, x0, #24, #4

	cmp	x0, #1

	b.ne	3f



	mrs	x0, ICC_SRE_EL2

	orr	x0, x0, #ICC_SRE_EL2_SRE	// Set ICC_SRE_EL2.SRE==1

	orr	x0, x0, #ICC_SRE_EL2_ENABLE	// Set ICC_SRE_EL2.Enable==1

	msr	ICC_SRE_EL2, x0

	isb					// Make sure SRE is now set

	msr	ICH_HCR_EL2, xzr		// Reset ICC_HCR_EL2 to defaults



3:

#endif



	/* Populate ID registers. */

	mrs	x0, midr_el1

	mrs	x1, mpidr_el1

arch/arm64/kernel/hyp-stub.S

+1 −0
Original line number Diff line number Diff line
@@ -19,6 +19,7 @@ 


#include <linux/init.h>

#include <linux/linkage.h>

#include <linux/irqchip/arm-gic-v3.h>



#include <asm/assembler.h>

#include <asm/ptrace.h>

drivers/irqchip/Kconfig

+5 −0
Original line number Diff line number Diff line
@@ -10,6 +10,11 @@ config ARM_GIC 
config GIC_NON_BANKED

	bool



config ARM_GIC_V3

	bool

	select IRQ_DOMAIN

	select MULTI_IRQ_HANDLER



config ARM_NVIC

	bool

	select IRQ_DOMAIN

drivers/irqchip/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ obj-$(CONFIG_ARCH_SUNXI) += irq-sun4i.o 
obj-$(CONFIG_ARCH_SUNXI)		+= irq-sunxi-nmi.o

obj-$(CONFIG_ARCH_SPEAR3XX)		+= spear-shirq.o

obj-$(CONFIG_ARM_GIC)			+= irq-gic.o irq-gic-common.o

obj-$(CONFIG_ARM_GIC_V3)		+= irq-gic-v3.o irq-gic-common.o

obj-$(CONFIG_ARM_NVIC)			+= irq-nvic.o

obj-$(CONFIG_ARM_VIC)			+= irq-vic.o

obj-$(CONFIG_IMGPDC_IRQ)		+= irq-imgpdc.o