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Commit 02044643 authored by Helmut Schaa's avatar Helmut Schaa Committed by John W. Linville
Browse files

rt2x00: Check for specific changed flags when updating the erp config 



Previously rt2x00 was always updating all erp related config variables
even though mac80211 might only have changed one. Hence, pass the
changed flags to the config_erp driver callback so that the driver
can limit the changes to the correct values.

This fixes an issue in AP mode where the beacon interval is not
initialized (and thus zero) but still sent to the hardware causing an
interrupt storm on rt2800pci hanging the system.

Signed-off-by: default avatarHelmut Schaa <helmut.schaa@googlemail.com>
Signed-off-by: default avatarIvo van Doorn <IvDoorn@gmail.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 47ee3eb1

drivers/net/wireless/rt2x00/rt2400pci.c

+64 −50
Original line number Diff line number Diff line
@@ -321,7 +321,8 @@ static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev, 
}



static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,

				 struct rt2x00lib_erp *erp)

				 struct rt2x00lib_erp *erp,

				 u32 changed)

{

	int preamble_mask;

	u32 reg;
@@ -329,6 +330,7 @@ static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev, 
	/*

	 * When short preamble is enabled, we should set bit 0x08

	 */

	if (changed & BSS_CHANGED_ERP_PREAMBLE) {

		preamble_mask = erp->short_preamble << 3;



		rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
@@ -341,38 +343,40 @@ static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev, 
		rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);

		rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);

		rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);

	rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 10));

		rt2x00_set_field32(&reg, ARCSR2_LENGTH,

				   GET_DURATION(ACK_SIZE, 10));

		rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);



		rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);

		rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);

		rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);

	rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 20));

		rt2x00_set_field32(&reg, ARCSR2_LENGTH,

				   GET_DURATION(ACK_SIZE, 20));

		rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);



		rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);

		rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);

		rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);

	rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 55));

		rt2x00_set_field32(&reg, ARCSR2_LENGTH,

				   GET_DURATION(ACK_SIZE, 55));

		rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);



		rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);

		rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);

		rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);

	rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 110));

		rt2x00_set_field32(&reg, ARCSR2_LENGTH,

				   GET_DURATION(ACK_SIZE, 110));

		rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);

	}



	if (changed & BSS_CHANGED_BASIC_RATES)

		rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);



	if (changed & BSS_CHANGED_ERP_SLOT) {

		rt2x00pci_register_read(rt2x00dev, CSR11, &reg);

		rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);

		rt2x00pci_register_write(rt2x00dev, CSR11, reg);



	rt2x00pci_register_read(rt2x00dev, CSR12, &reg);

	rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL, erp->beacon_int * 16);

	rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION, erp->beacon_int * 16);

	rt2x00pci_register_write(rt2x00dev, CSR12, reg);



		rt2x00pci_register_read(rt2x00dev, CSR18, &reg);

		rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);

		rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
@@ -384,6 +388,16 @@ static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev, 
		rt2x00pci_register_write(rt2x00dev, CSR19, reg);

	}



	if (changed & BSS_CHANGED_BEACON_INT) {

		rt2x00pci_register_read(rt2x00dev, CSR12, &reg);

		rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,

				   erp->beacon_int * 16);

		rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,

				   erp->beacon_int * 16);

		rt2x00pci_register_write(rt2x00dev, CSR12, reg);

	}

}



static void rt2400pci_config_ant(struct rt2x00_dev *rt2x00dev,

				 struct antenna_setup *ant)

{

drivers/net/wireless/rt2x00/rt2500pci.c

+65 −50
Original line number Diff line number Diff line
@@ -327,7 +327,8 @@ static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev, 
}



static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev,

				 struct rt2x00lib_erp *erp)

				 struct rt2x00lib_erp *erp,

				 u32 changed)

{

	int preamble_mask;

	u32 reg;
@@ -335,6 +336,7 @@ static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev, 
	/*

	 * When short preamble is enabled, we should set bit 0x08

	 */

	if (changed & BSS_CHANGED_ERP_PREAMBLE) {

		preamble_mask = erp->short_preamble << 3;



		rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
@@ -347,38 +349,40 @@ static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev, 
		rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);

		rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);

		rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);

	rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 10));

		rt2x00_set_field32(&reg, ARCSR2_LENGTH,

				   GET_DURATION(ACK_SIZE, 10));

		rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);



		rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);

		rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);

		rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);

	rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 20));

		rt2x00_set_field32(&reg, ARCSR2_LENGTH,

				   GET_DURATION(ACK_SIZE, 20));

		rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);



		rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);

		rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);

		rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);

	rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 55));

		rt2x00_set_field32(&reg, ARCSR2_LENGTH,

				   GET_DURATION(ACK_SIZE, 55));

		rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);



		rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);

		rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);

		rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);

	rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 110));

		rt2x00_set_field32(&reg, ARCSR2_LENGTH,

				   GET_DURATION(ACK_SIZE, 110));

		rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);

	}



	if (changed & BSS_CHANGED_BASIC_RATES)

		rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);



	if (changed & BSS_CHANGED_ERP_SLOT) {

		rt2x00pci_register_read(rt2x00dev, CSR11, &reg);

		rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);

		rt2x00pci_register_write(rt2x00dev, CSR11, reg);



	rt2x00pci_register_read(rt2x00dev, CSR12, &reg);

	rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL, erp->beacon_int * 16);

	rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION, erp->beacon_int * 16);

	rt2x00pci_register_write(rt2x00dev, CSR12, reg);



		rt2x00pci_register_read(rt2x00dev, CSR18, &reg);

		rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);

		rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
@@ -390,6 +394,17 @@ static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev, 
		rt2x00pci_register_write(rt2x00dev, CSR19, reg);

	}



	if (changed & BSS_CHANGED_BEACON_INT) {

		rt2x00pci_register_read(rt2x00dev, CSR12, &reg);

		rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,

				   erp->beacon_int * 16);

		rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,

				   erp->beacon_int * 16);

		rt2x00pci_register_write(rt2x00dev, CSR12, reg);

	}



}



static void rt2500pci_config_ant(struct rt2x00_dev *rt2x00dev,

				 struct antenna_setup *ant)

{

drivers/net/wireless/rt2x00/rt2500usb.c

+22 −12
Original line number Diff line number Diff line
@@ -494,25 +494,35 @@ static void rt2500usb_config_intf(struct rt2x00_dev *rt2x00dev, 
}



static void rt2500usb_config_erp(struct rt2x00_dev *rt2x00dev,

				 struct rt2x00lib_erp *erp)

				 struct rt2x00lib_erp *erp,

				 u32 changed)

{

	u16 reg;



	if (changed & BSS_CHANGED_ERP_PREAMBLE) {

		rt2500usb_register_read(rt2x00dev, TXRX_CSR10, &reg);

		rt2x00_set_field16(&reg, TXRX_CSR10_AUTORESPOND_PREAMBLE,

				   !!erp->short_preamble);

		rt2500usb_register_write(rt2x00dev, TXRX_CSR10, reg);

	}



	rt2500usb_register_write(rt2x00dev, TXRX_CSR11, erp->basic_rates);

	if (changed & BSS_CHANGED_BASIC_RATES)

		rt2500usb_register_write(rt2x00dev, TXRX_CSR11,

					 erp->basic_rates);



	if (changed & BSS_CHANGED_BEACON_INT) {

		rt2500usb_register_read(rt2x00dev, TXRX_CSR18, &reg);

	rt2x00_set_field16(&reg, TXRX_CSR18_INTERVAL, erp->beacon_int * 4);

		rt2x00_set_field16(&reg, TXRX_CSR18_INTERVAL,

				   erp->beacon_int * 4);

		rt2500usb_register_write(rt2x00dev, TXRX_CSR18, reg);

	}



	if (changed & BSS_CHANGED_ERP_SLOT) {

		rt2500usb_register_write(rt2x00dev, MAC_CSR10, erp->slot_time);

		rt2500usb_register_write(rt2x00dev, MAC_CSR11, erp->sifs);

		rt2500usb_register_write(rt2x00dev, MAC_CSR12, erp->eifs);

	}

}



static void rt2500usb_config_ant(struct rt2x00_dev *rt2x00dev,

				 struct antenna_setup *ant)

drivers/net/wireless/rt2x00/rt2800lib.c

+36 −24
Original line number Diff line number Diff line
@@ -1159,39 +1159,51 @@ void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf, 
}

EXPORT_SYMBOL_GPL(rt2800_config_intf);



void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp)

void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,

		       u32 changed)

{

	u32 reg;



	if (changed & BSS_CHANGED_ERP_PREAMBLE) {

		rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);

		rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,

				   !!erp->short_preamble);

		rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,

				   !!erp->short_preamble);

		rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);

	}



	if (changed & BSS_CHANGED_ERP_CTS_PROT) {

		rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);

		rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,

				   erp->cts_protection ? 2 : 0);

		rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);

	}



	if (changed & BSS_CHANGED_BASIC_RATES) {

		rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,

					 erp->basic_rates);

		rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);

	}



	if (changed & BSS_CHANGED_ERP_SLOT) {

		rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);

	rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);

		rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,

				   erp->slot_time);

		rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);



		rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);

		rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);

		rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);

	}



	if (changed & BSS_CHANGED_BEACON_INT) {

		rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);

		rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,

				   erp->beacon_int * 16);

		rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);

	}

}

EXPORT_SYMBOL_GPL(rt2800_config_erp);



void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)

drivers/net/wireless/rt2x00/rt2800lib.h

+2 −1
Original line number Diff line number Diff line
@@ -169,7 +169,8 @@ void rt2800_config_filter(struct rt2x00_dev *rt2x00dev, 
			  const unsigned int filter_flags);

void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,

			struct rt2x00intf_conf *conf, const unsigned int flags);

void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp);

void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,

		       u32 changed);

void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant);

void rt2800_config(struct rt2x00_dev *rt2x00dev,

		   struct rt2x00lib_conf *libconf,