Merge branch 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm

* ARM L2 Cache Controller

ARM cores often have a separate level 2 cache controller. There are various

implementations of the L2 cache controller with compatible programming models.

ARM cores often have a separate L2C210/L2C220/L2C310 (also known as PL210/PL220/

PL310 and variants) based level 2 cache controller. All these various implementations

of the L2 cache controller have compatible programming models (Note 1).

Some of the properties that are just prefixed "cache-*" are taken from section

3.7.3 of the ePAPR v1.1 specification which can be found at:

https://www.power.org/wp-content/uploads/2012/06/Power_ePAPR_APPROVED_v1.1.pdf

  disable if zero.

- arm,prefetch-offset : Override prefetch offset value. Valid values are

  0-7, 15, 23, and 31.

- arm,shared-override : The default behavior of the pl310 cache controller with

  respect to the shareable attribute is to transform "normal memory

  non-cacheable transactions" into "cacheable no allocate" (for reads) or

  "write through no write allocate" (for writes).

- arm,shared-override : The default behavior of the L220 or PL310 cache

  controllers with respect to the shareable attribute is to transform "normal

  memory non-cacheable transactions" into "cacheable no allocate" (for reads)

  or "write through no write allocate" (for writes).

  On systems where this may cause DMA buffer corruption, this property must be

  specified to indicate that such transforms are precluded.

- arm,parity-enable : enable parity checking on the L2 cache (L220 or PL310).

- arm,parity-disable : disable parity checking on the L2 cache (L220 or PL310).

- arm,outer-sync-disable : disable the outer sync operation on the L2 cache.

  Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that

  will randomly hang unless outer sync operations are disabled.

- prefetch-data : Data prefetch. Value: <0> (forcibly disable), <1>

  (forcibly enable), property absent (retain settings set by firmware)

- prefetch-instr : Instruction prefetch. Value: <0> (forcibly disable),

        cache-level = <2>;

	interrupts = <45>;

};

Note 1: The description in this document doesn't apply to integrated L2

	cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These

	integrated L2 controllers are assumed to be all preconfigured by

	early secure boot code. Thus no need to deal with their configuration

	in the kernel at all.

	select GENERIC_ALLOCATOR

	select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)

	select GENERIC_CLOCKEVENTS_BROADCAST if SMP

	select GENERIC_EARLY_IOREMAP

	select GENERIC_IDLE_POLL_SETUP

	select GENERIC_IRQ_PROBE

	select GENERIC_IRQ_SHOW

	select HARDIRQS_SW_RESEND

	select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)

	select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6

	select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32

	select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32

	select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU

	select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU

	select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)

	select HAVE_ARCH_TRACEHOOK

	select HAVE_ARM_SMCCC if CPU_V7

	select HAVE_BPF_JIT

	select HAVE_CC_STACKPROTECTOR

	select HAVE_CONTEXT_TRACKING

	select HAVE_DMA_API_DEBUG

	select HAVE_DMA_ATTRS

	select HAVE_DMA_CONTIGUOUS if MMU

	select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32

	select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU

	select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU

	select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)

	select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)

	bool "Dummy Virtual Machine" if ARCH_MULTI_V7

	select ARM_AMBA

	select ARM_GIC

	select ARM_GIC_V2M if PCI_MSI

	select ARM_GIC_V3

	select ARM_PSCI

	select HAVE_ARM_ARCH_TIMER

config BL_SWITCHER

	bool "big.LITTLE switcher support"

	depends on BIG_LITTLE && MCPM && HOTPLUG_CPU

	depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC

	select ARM_CPU_SUSPEND

	select CPU_PM

	help

config ARM_PSCI

	bool "Support for the ARM Power State Coordination Interface (PSCI)"

	depends on CPU_V7

	depends on HAVE_ARM_SMCCC

	select ARM_PSCI_FW

	help

	  Say Y here if you want Linux to communicate with system firmware

config ARM_ASM_UNIFIED

	bool

config ARM_PATCH_IDIV

	bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"

	depends on CPU_32v7 && !XIP_KERNEL

	default y

	help

	  The ARM compiler inserts calls to __aeabi_idiv() and

	  __aeabi_uidiv() when it needs to perform division on signed

	  and unsigned integers. Some v7 CPUs have support for the sdiv

	  and udiv instructions that can be used to implement those

	  functions.

	  Enabling this option allows the kernel to modify itself to

	  replace the first two instructions of these library functions

	  with the sdiv or udiv plus "bx lr" instructions when the CPU

	  it is running on supports them. Typically this will be faster

	  and less power intensive than running the original library

	  code to do integer division.

config AEABI

	bool "Use the ARM EABI to compile the kernel"

	help

	  0xf8000000. This assumes the zImage being placed in the first 128MB

	  from start of memory.

config EFI_STUB

	bool

config EFI

	bool "UEFI runtime support"

	depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL

	select UCS2_STRING

	select EFI_PARAMS_FROM_FDT

	select EFI_STUB

	select EFI_ARMSTUB

	select EFI_RUNTIME_WRAPPERS

	---help---

	  This option provides support for runtime services provided

	  by UEFI firmware (such as non-volatile variables, realtime

	  clock, and platform reset). A UEFI stub is also provided to

	  allow the kernel to be booted as an EFI application. This

	  is only useful for kernels that may run on systems that have

	  UEFI firmware.

endmenu

menu "CPU Power Management"

	false; \

fi

efi-obj-$(CONFIG_EFI_STUB) := $(objtree)/drivers/firmware/efi/libstub/lib.a

$(obj)/vmlinux: $(obj)/vmlinux.lds $(obj)/$(HEAD) $(obj)/piggy.$(suffix_y).o \

		$(addprefix $(obj)/, $(OBJS)) $(lib1funcs) $(ashldi3) \

		$(bswapsdi2) FORCE

		$(bswapsdi2) $(efi-obj-y) FORCE

	@$(check_for_multiple_zreladdr)

	$(call if_changed,ld)

	@$(check_for_bad_syms)

/*

 * Copyright (C) 2013-2015 Linaro Ltd

 * Authors: Roy Franz <roy.franz@linaro.org>

 *          Ard Biesheuvel <ard.biesheuvel@linaro.org>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 */

		.macro	__nop

#ifdef CONFIG_EFI_STUB

		@ This is almost but not quite a NOP, since it does clobber the

		@ condition flags. But it is the best we can do for EFI, since

		@ PE/COFF expects the magic string "MZ" at offset 0, while the

		@ ARM/Linux boot protocol expects an executable instruction

		@ there.

		.inst	'M' | ('Z' << 8) | (0x1310 << 16)   @ tstne r0, #0x4d000

#else

		mov	r0, r0

#endif

		.endm

		.macro	__EFI_HEADER

#ifdef CONFIG_EFI_STUB

		b	__efi_start

		.set	start_offset, __efi_start - start

		.org	start + 0x3c

		@

		@ The PE header can be anywhere in the file, but for

		@ simplicity we keep it together with the MSDOS header

		@ The offset to the PE/COFF header needs to be at offset

		@ 0x3C in the MSDOS header.

		@ The only 2 fields of the MSDOS header that are used are this

		@ PE/COFF offset, and the "MZ" bytes at offset 0x0.

		@

		.long	pe_header - start	@ Offset to the PE header.

pe_header:

		.ascii	"PE\0\0"

coff_header:

		.short	0x01c2			@ ARM or Thumb

		.short	2			@ nr_sections

		.long	0 			@ TimeDateStamp

		.long	0			@ PointerToSymbolTable

		.long	1			@ NumberOfSymbols

		.short	section_table - optional_header

						@ SizeOfOptionalHeader

		.short	0x306			@ Characteristics.

						@ IMAGE_FILE_32BIT_MACHINE |

						@ IMAGE_FILE_DEBUG_STRIPPED |

						@ IMAGE_FILE_EXECUTABLE_IMAGE |

						@ IMAGE_FILE_LINE_NUMS_STRIPPED

optional_header:

		.short	0x10b			@ PE32 format

		.byte	0x02			@ MajorLinkerVersion

		.byte	0x14			@ MinorLinkerVersion

		.long	_end - __efi_start	@ SizeOfCode

		.long	0			@ SizeOfInitializedData

		.long	0			@ SizeOfUninitializedData

		.long	efi_stub_entry - start	@ AddressOfEntryPoint

		.long	start_offset		@ BaseOfCode

		.long	0			@ data

extra_header_fields:

		.long	0			@ ImageBase

		.long	0x200			@ SectionAlignment

		.long	0x200			@ FileAlignment

		.short	0			@ MajorOperatingSystemVersion

		.short	0			@ MinorOperatingSystemVersion

		.short	0			@ MajorImageVersion

		.short	0			@ MinorImageVersion

		.short	0			@ MajorSubsystemVersion

		.short	0			@ MinorSubsystemVersion

		.long	0			@ Win32VersionValue

		.long	_end - start		@ SizeOfImage

		.long	start_offset		@ SizeOfHeaders

		.long	0			@ CheckSum

		.short	0xa			@ Subsystem (EFI application)

		.short	0			@ DllCharacteristics

		.long	0			@ SizeOfStackReserve

		.long	0			@ SizeOfStackCommit

		.long	0			@ SizeOfHeapReserve

		.long	0			@ SizeOfHeapCommit

		.long	0			@ LoaderFlags

		.long	0x6			@ NumberOfRvaAndSizes

		.quad	0			@ ExportTable

		.quad	0			@ ImportTable

		.quad	0			@ ResourceTable

		.quad	0			@ ExceptionTable

		.quad	0			@ CertificationTable

		.quad	0			@ BaseRelocationTable

section_table:

		@

		@ The EFI application loader requires a relocation section

		@ because EFI applications must be relocatable. This is a

		@ dummy section as far as we are concerned.

		@

		.ascii	".reloc\0\0"

		.long	0			@ VirtualSize

		.long	0			@ VirtualAddress

		.long	0			@ SizeOfRawData

		.long	0			@ PointerToRawData

		.long	0			@ PointerToRelocations

		.long	0			@ PointerToLineNumbers

		.short	0			@ NumberOfRelocations

		.short	0			@ NumberOfLineNumbers

		.long	0x42100040		@ Characteristics

		.ascii	".text\0\0\0"

		.long	_end - __efi_start	@ VirtualSize

		.long	__efi_start		@ VirtualAddress

		.long	_edata - __efi_start	@ SizeOfRawData

		.long	__efi_start		@ PointerToRawData

		.long	0			@ PointerToRelocations

		.long	0			@ PointerToLineNumbers

		.short	0			@ NumberOfRelocations

		.short	0			@ NumberOfLineNumbers

		.long	0xe0500020		@ Characteristics

		.align	9

__efi_start:

#endif

		.endm

#include <asm/assembler.h>

#include <asm/v7m.h>

#include "efi-header.S"

 AR_CLASS(	.arch	armv7-a	)

 M_CLASS(	.arch	armv7-m	)

start:

		.type	start,#function

		.rept	7

		mov	r0, r0

		__nop

		.endr

   ARM(		mov	r0, r0		)

   ARM(		b	1f		)

		.word	0x04030201	@ endianness flag

 THUMB(		.thumb			)

1:

1:		__EFI_HEADER

 ARM_BE8(	setend	be		)	@ go BE8 if compiled for BE8

 AR_CLASS(	mrs	r9, cpsr	)

#ifdef CONFIG_ARM_VIRT_EXT

reloc_code_end:

#ifdef CONFIG_EFI_STUB

		.align	2

_start:		.long	start - .

ENTRY(efi_stub_entry)

		@ allocate space on stack for passing current zImage address

		@ and for the EFI stub to return of new entry point of

		@ zImage, as EFI stub may copy the kernel. Pointer address

		@ is passed in r2. r0 and r1 are passed through from the

		@ EFI firmware to efi_entry

		adr	ip, _start

		ldr	r3, [ip]

		add	r3, r3, ip

		stmfd	sp!, {r3, lr}

		mov	r2, sp			@ pass zImage address in r2

		bl	efi_entry

		@ Check for error return from EFI stub. r0 has FDT address

		@ or error code.

		cmn	r0, #1

		beq	efi_load_fail

		@ Preserve return value of efi_entry() in r4

		mov	r4, r0

		bl	cache_clean_flush

		bl	cache_off

		@ Set parameters for booting zImage according to boot protocol

		@ put FDT address in r2, it was returned by efi_entry()

		@ r1 is the machine type, and r0 needs to be 0

		mov	r0, #0

		mov	r1, #0xFFFFFFFF

		mov	r2, r4

		@ Branch to (possibly) relocated zImage that is in [sp]

		ldr	lr, [sp]

		ldr	ip, =start_offset

		add	lr, lr, ip

		mov	pc, lr				@ no mode switch

efi_load_fail:

		@ Return EFI_LOAD_ERROR to EFI firmware on error.

		ldr	r0, =0x80000001

		ldmfd	sp!, {ip, pc}

ENDPROC(efi_stub_entry)

#endif

		.align

		.section ".stack", "aw", %nobits

.L_user_stack:	.space	4096