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Commit 013cfc50 authored by Robert Richter's avatar Robert Richter
Browse files

oprofile/x86: remove OPROFILE_IBS config option 



OProfile support for IBS is now for several versions in the
kernel. The feature is stable now and the code can be activated
permanently.

As a side effect IBS now works also on nosmp configs.

Signed-off-by: default avatarRobert Richter <robert.richter@amd.com>
parent b309a294

arch/Kconfig

+0 −14
Original line number Diff line number Diff line
@@ -15,20 +15,6 @@ config OPROFILE 


	  If unsure, say N.



config OPROFILE_IBS

	bool "OProfile AMD IBS support (EXPERIMENTAL)"

	default n

	depends on OPROFILE && SMP && X86

	help

          Instruction-Based Sampling (IBS) is a new profiling

          technique that provides rich, precise program performance

          information. IBS is introduced by AMD Family10h processors

          (AMD Opteron Quad-Core processor "Barcelona") to overcome

          the limitations of conventional performance counter

          sampling.



	  If unsure, say N.



config OPROFILE_EVENT_MULTIPLEX

	bool "OProfile multiplexing support (EXPERIMENTAL)"

	default n

arch/x86/oprofile/op_model_amd.c

+1 −30
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ 
#include <asm/ptrace.h>

#include <asm/msr.h>

#include <asm/nmi.h>

#include <asm/apic.h>



#include "op_x86_model.h"

#include "op_counter.h"
@@ -43,8 +44,6 @@ 


static unsigned long reset_value[NUM_VIRT_COUNTERS];



#ifdef CONFIG_OPROFILE_IBS



/* IbsFetchCtl bits/masks */

#define IBS_FETCH_RAND_EN		(1ULL<<57)

#define IBS_FETCH_VAL			(1ULL<<49)
@@ -72,8 +71,6 @@ struct op_ibs_config { 


static struct op_ibs_config ibs_config;



#endif



#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX



static void op_mux_fill_in_addresses(struct op_msrs * const msrs)
@@ -185,8 +182,6 @@ static void op_amd_setup_ctrs(struct op_x86_model_spec const *model, 
	}

}



#ifdef CONFIG_OPROFILE_IBS



static inline void

op_amd_handle_ibs(struct pt_regs * const regs,

		  struct op_msrs const * const msrs)
@@ -272,15 +267,6 @@ static void op_amd_stop_ibs(void) 
		wrmsrl(MSR_AMD64_IBSOPCTL, 0);

}



#else



static inline void op_amd_handle_ibs(struct pt_regs * const regs,

				    struct op_msrs const * const msrs) { }

static inline void op_amd_start_ibs(void) { }

static inline void op_amd_stop_ibs(void) { }



#endif



static int op_amd_check_ctrs(struct pt_regs * const regs,

			     struct op_msrs const * const msrs)

{
@@ -355,8 +341,6 @@ static void op_amd_shutdown(struct op_msrs const * const msrs) 
	}

}



#ifdef CONFIG_OPROFILE_IBS



static u8 ibs_eilvt_off;



static inline void apic_init_ibs_nmi_per_cpu(void *arg)
@@ -507,19 +491,6 @@ static void op_amd_exit(void) 
	ibs_exit();

}



#else



/* no IBS support */



static int op_amd_init(struct oprofile_operations *ops)

{

	return 0;

}



static void op_amd_exit(void) {}



#endif /* CONFIG_OPROFILE_IBS */



struct op_x86_model_spec op_amd_spec = {

	.num_counters		= NUM_COUNTERS,

	.num_controls		= NUM_CONTROLS,