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Commit 00fc31b7 authored by Chon Ming Lee's avatar Chon Ming Lee Committed by Daniel Vetter
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drm/i915/chv: Update Cherryview DPLL changes to support Port D. v2 



The additional DPLL registers added to support Port D.  Besides, add
some new PHY control and status registers based on B-spec.

v2: Based on Ville review
	- Corrected DPIO_PHY_STATUS offset and name.
    - Rebase based on upstream change after introduce enum dpio_phy and
      enum dpio_channel.

v3: Rebased on top of Antti's 3-pipe prep patch. Note that the new offsets for
the DPLL registers aren't in place yet, so this introduces a slight regression.
But since 3 pipe support isn't fully enabled yet anyaway in -internal this
shouldn't matter too much.

Signed-off-by: default avatarChon Ming Lee <chon.ming.lee@intel.com>
Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent a09caddd

drivers/gpu/drm/i915/i915_reg.h

+6 −0
Original line number Diff line number Diff line
@@ -29,6 +29,8 @@ 
#define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a)))



#define _PORT(port, a, b) ((a) + (port)*((b)-(a)))

#define _PIPE3(pipe, a, b, c) (pipe < 2 ? _PIPE(pipe, a, b) : c)

#define _PORT3(port, a, b, c) (port < 2 ? _PORT(port, a, b) : c)



#define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a))

#define _MASKED_BIT_DISABLE(a) ((a) << 16)
@@ -1417,6 +1419,10 @@ enum punit_power_well { 
#define   DPLL_PORTB_READY_MASK		(0xf)



#define   DPLL_FPA01_P1_POST_DIV_MASK_I830	0x001f0000



/* Additional CHV pll/phy registers */

#define DPIO_PHY_STATUS			(VLV_DISPLAY_BASE + 0x6240)

#define   DPLL_PORTD_READY_MASK		(0xf)

/*

 * The i830 generation, in LVDS mode, defines P1 as the bit number set within

 * this field (only one bit may be set).

drivers/gpu/drm/i915/intel_display.c

+9 −2
Original line number Diff line number Diff line
@@ -1535,21 +1535,28 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv, 
		struct intel_digital_port *dport)

{

	u32 port_mask;

	int dpll_reg;



	switch (dport->port) {

	case PORT_B:

		port_mask = DPLL_PORTB_READY_MASK;

		dpll_reg = DPLL(0);

		break;

	case PORT_C:

		port_mask = DPLL_PORTC_READY_MASK;

		dpll_reg = DPLL(0);

		break;

	case PORT_D:

		port_mask = DPLL_PORTD_READY_MASK;

		dpll_reg = DPIO_PHY_STATUS;

		break;

	default:

		BUG();

	}



	if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))

	if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))

		WARN(1, "timed out waiting for port %c ready: 0x%08x\n",

		     port_name(dport->port), I915_READ(DPLL(0)));

		     port_name(dport->port), I915_READ(dpll_reg));

}



/**

drivers/gpu/drm/i915/intel_drv.h

+1 −0
Original line number Diff line number Diff line
@@ -561,6 +561,7 @@ vlv_dport_to_channel(struct intel_digital_port *dport) 
{

	switch (dport->port) {

	case PORT_B:

	case PORT_D:

		return DPIO_CH0;

	case PORT_C:

		return DPIO_CH1;