Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit ffa05e45 authored by Laxman Dewangan's avatar Laxman Dewangan Committed by Stephen Warren
Browse files

ARM: tegra: Add OF_DEV_AUXDATA for SLINK driver in board dt 



Add OF_DEV_AUXDATA for slink driver for Tegra20 and Tegra30
board dt files.
Set the parent clock of slink controller to PLLP and configure
clock to 100MHz.

Signed-off-by: default avatarLaxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
parent d065ab71

arch/arm/mach-tegra/board-dt-tegra20.c

+8 −0
Original line number Diff line number Diff line
@@ -89,6 +89,10 @@ struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = { 
		       &tegra_ehci3_pdata),

	OF_DEV_AUXDATA("nvidia,tegra20-apbdma", TEGRA_APB_DMA_BASE, "tegra-apbdma", NULL),

	OF_DEV_AUXDATA("nvidia,tegra20-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL),

	OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D400, "spi_tegra.0", NULL),

	OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D600, "spi_tegra.1", NULL),

	OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D800, "spi_tegra.2", NULL),

	OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000DA00, "spi_tegra.3", NULL),

	{}

};
@@ -108,6 +112,10 @@ static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = { 
	{ "sdmmc1",	"pll_p",	48000000,	false},

	{ "sdmmc3",	"pll_p",	48000000,	false},

	{ "sdmmc4",	"pll_p",	48000000,	false},

	{ "sbc1",	"pll_p",	100000000,	false },

	{ "sbc2",	"pll_p",	100000000,	false },

	{ "sbc3",	"pll_p",	100000000,	false },

	{ "sbc4",	"pll_p",	100000000,	false },

	{ NULL,		NULL,		0,		0},

};

arch/arm/mach-tegra/board-dt-tegra30.c

+12 −0
Original line number Diff line number Diff line
@@ -51,6 +51,12 @@ struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = { 
	OF_DEV_AUXDATA("nvidia,tegra30-ahub", 0x70080000, "tegra30-ahub", NULL),

	OF_DEV_AUXDATA("nvidia,tegra30-apbdma", 0x6000a000, "tegra-apbdma", NULL),

	OF_DEV_AUXDATA("nvidia,tegra30-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL),

	OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000D400, "spi_tegra.0", NULL),

	OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000D600, "spi_tegra.1", NULL),

	OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000D800, "spi_tegra.2", NULL),

	OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DA00, "spi_tegra.3", NULL),

	OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DC00, "spi_tegra.4", NULL),

	OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DE00, "spi_tegra.5", NULL),

	{}

};
@@ -70,6 +76,12 @@ static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = { 
	{ "sdmmc1",	"pll_p",	48000000,	false},

	{ "sdmmc3",	"pll_p",	48000000,	false},

	{ "sdmmc4",	"pll_p",	48000000,	false},

	{ "sbc1",	"pll_p",	100000000,	false},

	{ "sbc2",	"pll_p",	100000000,	false},

	{ "sbc3",	"pll_p",	100000000,	false},

	{ "sbc4",	"pll_p",	100000000,	false},

	{ "sbc5",	"pll_p",	100000000,	false},

	{ "sbc6",	"pll_p",	100000000,	false},

	{ NULL,		NULL,		0,		0},

};