Loading Documentation/arm64/silicon-errata.txt +1 −0 Original line number Diff line number Diff line Loading @@ -56,3 +56,4 @@ stable kernels. | | | | | | Cavium | ThunderX ITS | #22375, #24313 | CAVIUM_ERRATUM_22375 | | Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 | | Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 | android/configs/android-base.cfg +1 −0 Original line number Diff line number Diff line Loading @@ -24,6 +24,7 @@ CONFIG_DM_VERITY=y CONFIG_DM_VERITY_FEC=y CONFIG_EMBEDDED=y CONFIG_FB=y CONFIG_HARDENED_USERCOPY=y CONFIG_HIGH_RES_TIMERS=y CONFIG_INET6_AH=y CONFIG_INET6_ESP=y Loading arch/arm64/Kconfig +8 −0 Original line number Diff line number Diff line Loading @@ -715,6 +715,14 @@ config SETEND_EMULATION If unsure, say Y endif config ARM64_SW_TTBR0_PAN bool "Emulate Priviledged Access Never using TTBR0_EL1 switching" help Enabling this option prevents the kernel from accessing user-space memory directly by pointing TTBR0_EL1 to a reserved zeroed area and reserved ASID. The user access routines restore the valid TTBR0_EL1 temporarily. menu "ARMv8.1 architectural features" config ARM64_HW_AFDBM Loading arch/arm64/include/asm/alternative.h +7 −9 Original line number Diff line number Diff line Loading @@ -95,13 +95,11 @@ void apply_alternatives(void *start, size_t length); * The code that follows this macro will be assembled and linked as * normal. There are no restrictions on this code. */ .macro alternative_if_not cap, enable = 1 .if \enable .macro alternative_if_not cap .pushsection .altinstructions, "a" altinstruction_entry 661f, 663f, \cap, 662f-661f, 664f-663f .popsection 661: .endif .endm /* Loading @@ -118,27 +116,27 @@ void apply_alternatives(void *start, size_t length); * alternative sequence it is defined in (branches into an * alternative sequence are not fixed up). */ .macro alternative_else, enable = 1 .if \enable .macro alternative_else 662: .pushsection .altinstr_replacement, "ax" 663: .endif .endm /* * Complete an alternative code sequence. */ .macro alternative_endif, enable = 1 .if \enable .macro alternative_endif 664: .popsection .org . - (664b-663b) + (662b-661b) .org . - (662b-661b) + (664b-663b) .endif .endm #define _ALTERNATIVE_CFG(insn1, insn2, cap, cfg, ...) \ alternative_insn insn1, insn2, cap, IS_ENABLED(cfg) .macro user_alt, label, oldinstr, newinstr, cond 9999: alternative_insn "\oldinstr", "\newinstr", \cond _ASM_EXTABLE 9999b, \label .endm /* * Generate the assembly for UAO alternatives with exception table entries. Loading arch/arm64/include/asm/assembler.h +163 −1 Original line number Diff line number Diff line /* * Based on arch/arm/include/asm/assembler.h * Based on arch/arm/include/asm/assembler.h, arch/arm/mm/proc-macros.S * * Copyright (C) 1996-2000 Russell King * Copyright (C) 2012 ARM Ltd. Loading @@ -23,6 +23,10 @@ #ifndef __ASM_ASSEMBLER_H #define __ASM_ASSEMBLER_H #include <asm/asm-offsets.h> #include <asm/cpufeature.h> #include <asm/page.h> #include <asm/pgtable-hwdef.h> #include <asm/ptrace.h> #include <asm/thread_info.h> Loading @@ -49,6 +53,15 @@ msr daifclr, #2 .endm .macro save_and_disable_irq, flags mrs \flags, daif msr daifset, #2 .endm .macro restore_irq, flags msr daif, \flags .endm /* * Enable and disable debug exceptions. */ Loading Loading @@ -211,6 +224,111 @@ lr .req x30 // link register add \reg, \reg, \tmp .endm /* * vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm) */ .macro vma_vm_mm, rd, rn ldr \rd, [\rn, #VMA_VM_MM] .endm /* * mmid - get context id from mm pointer (mm->context.id) */ .macro mmid, rd, rn ldr \rd, [\rn, #MM_CONTEXT_ID] .endm /* * dcache_line_size - get the minimum D-cache line size from the CTR register. */ .macro dcache_line_size, reg, tmp mrs \tmp, ctr_el0 // read CTR ubfm \tmp, \tmp, #16, #19 // cache line size encoding mov \reg, #4 // bytes per word lsl \reg, \reg, \tmp // actual cache line size .endm /* * icache_line_size - get the minimum I-cache line size from the CTR register. */ .macro icache_line_size, reg, tmp mrs \tmp, ctr_el0 // read CTR and \tmp, \tmp, #0xf // cache line size encoding mov \reg, #4 // bytes per word lsl \reg, \reg, \tmp // actual cache line size .endm /* * tcr_set_idmap_t0sz - update TCR.T0SZ so that we can load the ID map */ .macro tcr_set_idmap_t0sz, valreg, tmpreg #ifndef CONFIG_ARM64_VA_BITS_48 ldr_l \tmpreg, idmap_t0sz bfi \valreg, \tmpreg, #TCR_T0SZ_OFFSET, #TCR_TxSZ_WIDTH #endif .endm /* * Macro to perform a data cache maintenance for the interval * [kaddr, kaddr + size) * * op: operation passed to dc instruction * domain: domain used in dsb instruciton * kaddr: starting virtual address of the region * size: size of the region * Corrupts: kaddr, size, tmp1, tmp2 */ .macro dcache_by_line_op op, domain, kaddr, size, tmp1, tmp2 dcache_line_size \tmp1, \tmp2 add \size, \kaddr, \size sub \tmp2, \tmp1, #1 bic \kaddr, \kaddr, \tmp2 9998: .if (\op == cvau || \op == cvac) alternative_if_not ARM64_WORKAROUND_CLEAN_CACHE dc \op, \kaddr alternative_else dc civac, \kaddr alternative_endif .else dc \op, \kaddr .endif add \kaddr, \kaddr, \tmp1 cmp \kaddr, \size b.lo 9998b dsb \domain .endm /* * reset_pmuserenr_el0 - reset PMUSERENR_EL0 if PMUv3 present */ .macro reset_pmuserenr_el0, tmpreg mrs \tmpreg, id_aa64dfr0_el1 // Check ID_AA64DFR0_EL1 PMUVer sbfx \tmpreg, \tmpreg, #8, #4 cmp \tmpreg, #1 // Skip if no PMU present b.lt 9000f msr pmuserenr_el0, xzr // Disable PMU access from EL0 9000: .endm /* * copy_page - copy src to dest using temp registers t1-t8 */ .macro copy_page dest:req src:req t1:req t2:req t3:req t4:req t5:req t6:req t7:req t8:req 9998: ldp \t1, \t2, [\src] ldp \t3, \t4, [\src, #16] ldp \t5, \t6, [\src, #32] ldp \t7, \t8, [\src, #48] add \src, \src, #64 stnp \t1, \t2, [\dest] stnp \t3, \t4, [\dest, #16] stnp \t5, \t6, [\dest, #32] stnp \t7, \t8, [\dest, #48] add \dest, \dest, #64 tst \src, #(PAGE_SIZE - 1) b.ne 9998b .endm /* * Annotate a function as position independent, i.e., safe to be called before * the kernel virtual mapping is activated. Loading @@ -233,4 +351,48 @@ lr .req x30 // link register .long \sym\()_hi32 .endm /* * mov_q - move an immediate constant into a 64-bit register using * between 2 and 4 movz/movk instructions (depending on the * magnitude and sign of the operand) */ .macro mov_q, reg, val .if (((\val) >> 31) == 0 || ((\val) >> 31) == 0x1ffffffff) movz \reg, :abs_g1_s:\val .else .if (((\val) >> 47) == 0 || ((\val) >> 47) == 0x1ffff) movz \reg, :abs_g2_s:\val .else movz \reg, :abs_g3:\val movk \reg, :abs_g2_nc:\val .endif movk \reg, :abs_g1_nc:\val .endif movk \reg, :abs_g0_nc:\val .endm /* * Return the current thread_info. */ .macro get_thread_info, rd mrs \rd, sp_el0 .endm /* * Errata workaround post TTBR0_EL1 update. */ .macro post_ttbr0_update_workaround #ifdef CONFIG_CAVIUM_ERRATUM_27456 alternative_if_not ARM64_WORKAROUND_CAVIUM_27456 nop nop nop alternative_else ic iallu dsb nsh isb alternative_endif #endif .endm #endif /* __ASM_ASSEMBLER_H */ Loading
Documentation/arm64/silicon-errata.txt +1 −0 Original line number Diff line number Diff line Loading @@ -56,3 +56,4 @@ stable kernels. | | | | | | Cavium | ThunderX ITS | #22375, #24313 | CAVIUM_ERRATUM_22375 | | Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 | | Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 |
android/configs/android-base.cfg +1 −0 Original line number Diff line number Diff line Loading @@ -24,6 +24,7 @@ CONFIG_DM_VERITY=y CONFIG_DM_VERITY_FEC=y CONFIG_EMBEDDED=y CONFIG_FB=y CONFIG_HARDENED_USERCOPY=y CONFIG_HIGH_RES_TIMERS=y CONFIG_INET6_AH=y CONFIG_INET6_ESP=y Loading
arch/arm64/Kconfig +8 −0 Original line number Diff line number Diff line Loading @@ -715,6 +715,14 @@ config SETEND_EMULATION If unsure, say Y endif config ARM64_SW_TTBR0_PAN bool "Emulate Priviledged Access Never using TTBR0_EL1 switching" help Enabling this option prevents the kernel from accessing user-space memory directly by pointing TTBR0_EL1 to a reserved zeroed area and reserved ASID. The user access routines restore the valid TTBR0_EL1 temporarily. menu "ARMv8.1 architectural features" config ARM64_HW_AFDBM Loading
arch/arm64/include/asm/alternative.h +7 −9 Original line number Diff line number Diff line Loading @@ -95,13 +95,11 @@ void apply_alternatives(void *start, size_t length); * The code that follows this macro will be assembled and linked as * normal. There are no restrictions on this code. */ .macro alternative_if_not cap, enable = 1 .if \enable .macro alternative_if_not cap .pushsection .altinstructions, "a" altinstruction_entry 661f, 663f, \cap, 662f-661f, 664f-663f .popsection 661: .endif .endm /* Loading @@ -118,27 +116,27 @@ void apply_alternatives(void *start, size_t length); * alternative sequence it is defined in (branches into an * alternative sequence are not fixed up). */ .macro alternative_else, enable = 1 .if \enable .macro alternative_else 662: .pushsection .altinstr_replacement, "ax" 663: .endif .endm /* * Complete an alternative code sequence. */ .macro alternative_endif, enable = 1 .if \enable .macro alternative_endif 664: .popsection .org . - (664b-663b) + (662b-661b) .org . - (662b-661b) + (664b-663b) .endif .endm #define _ALTERNATIVE_CFG(insn1, insn2, cap, cfg, ...) \ alternative_insn insn1, insn2, cap, IS_ENABLED(cfg) .macro user_alt, label, oldinstr, newinstr, cond 9999: alternative_insn "\oldinstr", "\newinstr", \cond _ASM_EXTABLE 9999b, \label .endm /* * Generate the assembly for UAO alternatives with exception table entries. Loading
arch/arm64/include/asm/assembler.h +163 −1 Original line number Diff line number Diff line /* * Based on arch/arm/include/asm/assembler.h * Based on arch/arm/include/asm/assembler.h, arch/arm/mm/proc-macros.S * * Copyright (C) 1996-2000 Russell King * Copyright (C) 2012 ARM Ltd. Loading @@ -23,6 +23,10 @@ #ifndef __ASM_ASSEMBLER_H #define __ASM_ASSEMBLER_H #include <asm/asm-offsets.h> #include <asm/cpufeature.h> #include <asm/page.h> #include <asm/pgtable-hwdef.h> #include <asm/ptrace.h> #include <asm/thread_info.h> Loading @@ -49,6 +53,15 @@ msr daifclr, #2 .endm .macro save_and_disable_irq, flags mrs \flags, daif msr daifset, #2 .endm .macro restore_irq, flags msr daif, \flags .endm /* * Enable and disable debug exceptions. */ Loading Loading @@ -211,6 +224,111 @@ lr .req x30 // link register add \reg, \reg, \tmp .endm /* * vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm) */ .macro vma_vm_mm, rd, rn ldr \rd, [\rn, #VMA_VM_MM] .endm /* * mmid - get context id from mm pointer (mm->context.id) */ .macro mmid, rd, rn ldr \rd, [\rn, #MM_CONTEXT_ID] .endm /* * dcache_line_size - get the minimum D-cache line size from the CTR register. */ .macro dcache_line_size, reg, tmp mrs \tmp, ctr_el0 // read CTR ubfm \tmp, \tmp, #16, #19 // cache line size encoding mov \reg, #4 // bytes per word lsl \reg, \reg, \tmp // actual cache line size .endm /* * icache_line_size - get the minimum I-cache line size from the CTR register. */ .macro icache_line_size, reg, tmp mrs \tmp, ctr_el0 // read CTR and \tmp, \tmp, #0xf // cache line size encoding mov \reg, #4 // bytes per word lsl \reg, \reg, \tmp // actual cache line size .endm /* * tcr_set_idmap_t0sz - update TCR.T0SZ so that we can load the ID map */ .macro tcr_set_idmap_t0sz, valreg, tmpreg #ifndef CONFIG_ARM64_VA_BITS_48 ldr_l \tmpreg, idmap_t0sz bfi \valreg, \tmpreg, #TCR_T0SZ_OFFSET, #TCR_TxSZ_WIDTH #endif .endm /* * Macro to perform a data cache maintenance for the interval * [kaddr, kaddr + size) * * op: operation passed to dc instruction * domain: domain used in dsb instruciton * kaddr: starting virtual address of the region * size: size of the region * Corrupts: kaddr, size, tmp1, tmp2 */ .macro dcache_by_line_op op, domain, kaddr, size, tmp1, tmp2 dcache_line_size \tmp1, \tmp2 add \size, \kaddr, \size sub \tmp2, \tmp1, #1 bic \kaddr, \kaddr, \tmp2 9998: .if (\op == cvau || \op == cvac) alternative_if_not ARM64_WORKAROUND_CLEAN_CACHE dc \op, \kaddr alternative_else dc civac, \kaddr alternative_endif .else dc \op, \kaddr .endif add \kaddr, \kaddr, \tmp1 cmp \kaddr, \size b.lo 9998b dsb \domain .endm /* * reset_pmuserenr_el0 - reset PMUSERENR_EL0 if PMUv3 present */ .macro reset_pmuserenr_el0, tmpreg mrs \tmpreg, id_aa64dfr0_el1 // Check ID_AA64DFR0_EL1 PMUVer sbfx \tmpreg, \tmpreg, #8, #4 cmp \tmpreg, #1 // Skip if no PMU present b.lt 9000f msr pmuserenr_el0, xzr // Disable PMU access from EL0 9000: .endm /* * copy_page - copy src to dest using temp registers t1-t8 */ .macro copy_page dest:req src:req t1:req t2:req t3:req t4:req t5:req t6:req t7:req t8:req 9998: ldp \t1, \t2, [\src] ldp \t3, \t4, [\src, #16] ldp \t5, \t6, [\src, #32] ldp \t7, \t8, [\src, #48] add \src, \src, #64 stnp \t1, \t2, [\dest] stnp \t3, \t4, [\dest, #16] stnp \t5, \t6, [\dest, #32] stnp \t7, \t8, [\dest, #48] add \dest, \dest, #64 tst \src, #(PAGE_SIZE - 1) b.ne 9998b .endm /* * Annotate a function as position independent, i.e., safe to be called before * the kernel virtual mapping is activated. Loading @@ -233,4 +351,48 @@ lr .req x30 // link register .long \sym\()_hi32 .endm /* * mov_q - move an immediate constant into a 64-bit register using * between 2 and 4 movz/movk instructions (depending on the * magnitude and sign of the operand) */ .macro mov_q, reg, val .if (((\val) >> 31) == 0 || ((\val) >> 31) == 0x1ffffffff) movz \reg, :abs_g1_s:\val .else .if (((\val) >> 47) == 0 || ((\val) >> 47) == 0x1ffff) movz \reg, :abs_g2_s:\val .else movz \reg, :abs_g3:\val movk \reg, :abs_g2_nc:\val .endif movk \reg, :abs_g1_nc:\val .endif movk \reg, :abs_g0_nc:\val .endm /* * Return the current thread_info. */ .macro get_thread_info, rd mrs \rd, sp_el0 .endm /* * Errata workaround post TTBR0_EL1 update. */ .macro post_ttbr0_update_workaround #ifdef CONFIG_CAVIUM_ERRATUM_27456 alternative_if_not ARM64_WORKAROUND_CAVIUM_27456 nop nop nop alternative_else ic iallu dsb nsh isb alternative_endif #endif .endm #endif /* __ASM_ASSEMBLER_H */
