Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit fed84102 authored by Govind Singh's avatar Govind Singh
Browse files

ath10k: Make CE layer bus agnostic 



Remove bus specific dependencies from CE layer to have
common CE layer across multiple targets.

Change-Id: Ieb6a80b359eed820653215bbf98148ce15634e87
Signed-off-by: default avatarGovind Singh <govinds@codeaurora.org>
parent 74e7bd58

drivers/net/wireless/ath/ath10k/ce.c

+68 −81
Original line number Diff line number Diff line
@@ -16,7 +16,6 @@ 
 */



#include "hif.h"

#include "pci.h"

#include "ce.h"

#include "debug.h"
@@ -63,56 +62,56 @@ static inline void ath10k_ce_dest_ring_write_index_set(struct ath10k *ar, 
						       u32 ce_ctrl_addr,

						       unsigned int n)

{

	ath10k_pci_write32(ar, ce_ctrl_addr + DST_WR_INDEX_ADDRESS, n);

	ar->bus_write32(ar, ce_ctrl_addr + DST_WR_INDEX_ADDRESS, n);

}



static inline u32 ath10k_ce_dest_ring_write_index_get(struct ath10k *ar,

						      u32 ce_ctrl_addr)

{

	return ath10k_pci_read32(ar, ce_ctrl_addr + DST_WR_INDEX_ADDRESS);

	return ar->bus_read32(ar, ce_ctrl_addr + DST_WR_INDEX_ADDRESS);

}



static inline void ath10k_ce_src_ring_write_index_set(struct ath10k *ar,

						      u32 ce_ctrl_addr,

						      unsigned int n)

{

	ath10k_pci_write32(ar, ce_ctrl_addr + SR_WR_INDEX_ADDRESS, n);

	ar->bus_write32(ar, ce_ctrl_addr + SR_WR_INDEX_ADDRESS, n);

}



static inline u32 ath10k_ce_src_ring_write_index_get(struct ath10k *ar,

						     u32 ce_ctrl_addr)

{

	return ath10k_pci_read32(ar, ce_ctrl_addr + SR_WR_INDEX_ADDRESS);

	return ar->bus_read32(ar, ce_ctrl_addr + SR_WR_INDEX_ADDRESS);

}



static inline u32 ath10k_ce_src_ring_read_index_get(struct ath10k *ar,

						    u32 ce_ctrl_addr)

{

	return ath10k_pci_read32(ar, ce_ctrl_addr + CURRENT_SRRI_ADDRESS);

	return ar->bus_read32(ar, ce_ctrl_addr + CURRENT_SRRI_ADDRESS);

}



static inline void ath10k_ce_src_ring_base_addr_set(struct ath10k *ar,

						    u32 ce_ctrl_addr,

						    unsigned int addr)

{

	ath10k_pci_write32(ar, ce_ctrl_addr + SR_BA_ADDRESS, addr);

	ar->bus_write32(ar, ce_ctrl_addr + SR_BA_ADDRESS, addr);

}



static inline void ath10k_ce_src_ring_size_set(struct ath10k *ar,

					       u32 ce_ctrl_addr,

					       unsigned int n)

{

	ath10k_pci_write32(ar, ce_ctrl_addr + SR_SIZE_ADDRESS, n);

	ar->bus_write32(ar, ce_ctrl_addr + SR_SIZE_ADDRESS, n);

}



static inline void ath10k_ce_src_ring_dmax_set(struct ath10k *ar,

					       u32 ce_ctrl_addr,

					       unsigned int n)

{

	u32 ctrl1_addr = ath10k_pci_read32((ar),

	u32 ctrl1_addr = ar->bus_read32((ar),

					   (ce_ctrl_addr) + CE_CTRL1_ADDRESS);



	ath10k_pci_write32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS,

	ar->bus_write32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS,

			   (ctrl1_addr &  ~CE_CTRL1_DMAX_LENGTH_MASK) |

			   CE_CTRL1_DMAX_LENGTH_SET(n));

}
@@ -121,9 +120,9 @@ static inline void ath10k_ce_src_ring_byte_swap_set(struct ath10k *ar, 
						    u32 ce_ctrl_addr,

						    unsigned int n)

{

	u32 ctrl1_addr = ath10k_pci_read32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS);

	u32 ctrl1_addr = ar->bus_read32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS);



	ath10k_pci_write32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS,

	ar->bus_write32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS,

			   (ctrl1_addr & ~CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) |

			   CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SET(n));

}
@@ -132,9 +131,9 @@ static inline void ath10k_ce_dest_ring_byte_swap_set(struct ath10k *ar, 
						     u32 ce_ctrl_addr,

						     unsigned int n)

{

	u32 ctrl1_addr = ath10k_pci_read32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS);

	u32 ctrl1_addr = ar->bus_read32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS);



	ath10k_pci_write32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS,

	ar->bus_write32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS,

			   (ctrl1_addr & ~CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK) |

			   CE_CTRL1_DST_RING_BYTE_SWAP_EN_SET(n));

}
@@ -142,30 +141,30 @@ static inline void ath10k_ce_dest_ring_byte_swap_set(struct ath10k *ar, 
static inline u32 ath10k_ce_dest_ring_read_index_get(struct ath10k *ar,

						     u32 ce_ctrl_addr)

{

	return ath10k_pci_read32(ar, ce_ctrl_addr + CURRENT_DRRI_ADDRESS);

	return ar->bus_read32(ar, ce_ctrl_addr + CURRENT_DRRI_ADDRESS);

}



static inline void ath10k_ce_dest_ring_base_addr_set(struct ath10k *ar,

						     u32 ce_ctrl_addr,

						     u32 addr)

{

	ath10k_pci_write32(ar, ce_ctrl_addr + DR_BA_ADDRESS, addr);

	ar->bus_write32(ar, ce_ctrl_addr + DR_BA_ADDRESS, addr);

}



static inline void ath10k_ce_dest_ring_size_set(struct ath10k *ar,

						u32 ce_ctrl_addr,

						unsigned int n)

{

	ath10k_pci_write32(ar, ce_ctrl_addr + DR_SIZE_ADDRESS, n);

	ar->bus_write32(ar, ce_ctrl_addr + DR_SIZE_ADDRESS, n);

}



static inline void ath10k_ce_src_ring_highmark_set(struct ath10k *ar,

						   u32 ce_ctrl_addr,

						   unsigned int n)

{

	u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS);

	u32 addr = ar->bus_read32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS);



	ath10k_pci_write32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS,

	ar->bus_write32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS,

			   (addr & ~SRC_WATERMARK_HIGH_MASK) |

			   SRC_WATERMARK_HIGH_SET(n));

}
@@ -174,9 +173,9 @@ static inline void ath10k_ce_src_ring_lowmark_set(struct ath10k *ar, 
						  u32 ce_ctrl_addr,

						  unsigned int n)

{

	u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS);

	u32 addr = ar->bus_read32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS);



	ath10k_pci_write32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS,

	ar->bus_write32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS,

			   (addr & ~SRC_WATERMARK_LOW_MASK) |

			   SRC_WATERMARK_LOW_SET(n));

}
@@ -185,9 +184,9 @@ static inline void ath10k_ce_dest_ring_highmark_set(struct ath10k *ar, 
						    u32 ce_ctrl_addr,

						    unsigned int n)

{

	u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS);

	u32 addr = ar->bus_read32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS);



	ath10k_pci_write32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS,

	ar->bus_write32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS,

			   (addr & ~DST_WATERMARK_HIGH_MASK) |

			   DST_WATERMARK_HIGH_SET(n));

}
@@ -196,9 +195,9 @@ static inline void ath10k_ce_dest_ring_lowmark_set(struct ath10k *ar, 
						   u32 ce_ctrl_addr,

						   unsigned int n)

{

	u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS);

	u32 addr = ar->bus_read32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS);



	ath10k_pci_write32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS,

	ar->bus_write32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS,

			   (addr & ~DST_WATERMARK_LOW_MASK) |

			   DST_WATERMARK_LOW_SET(n));

}
@@ -206,50 +205,50 @@ static inline void ath10k_ce_dest_ring_lowmark_set(struct ath10k *ar, 
static inline void ath10k_ce_copy_complete_inter_enable(struct ath10k *ar,

							u32 ce_ctrl_addr)

{

	u32 host_ie_addr = ath10k_pci_read32(ar,

	u32 host_ie_addr = ar->bus_read32(ar,

					     ce_ctrl_addr + HOST_IE_ADDRESS);



	ath10k_pci_write32(ar, ce_ctrl_addr + HOST_IE_ADDRESS,

	ar->bus_write32(ar, ce_ctrl_addr + HOST_IE_ADDRESS,

			   host_ie_addr | HOST_IE_COPY_COMPLETE_MASK);

}



static inline void ath10k_ce_copy_complete_intr_disable(struct ath10k *ar,

							u32 ce_ctrl_addr)

{

	u32 host_ie_addr = ath10k_pci_read32(ar,

	u32 host_ie_addr = ar->bus_read32(ar,

					     ce_ctrl_addr + HOST_IE_ADDRESS);



	ath10k_pci_write32(ar, ce_ctrl_addr + HOST_IE_ADDRESS,

	ar->bus_write32(ar, ce_ctrl_addr + HOST_IE_ADDRESS,

			   host_ie_addr & ~HOST_IE_COPY_COMPLETE_MASK);

}



static inline void ath10k_ce_watermark_intr_disable(struct ath10k *ar,

						    u32 ce_ctrl_addr)

{

	u32 host_ie_addr = ath10k_pci_read32(ar,

	u32 host_ie_addr = ar->bus_read32(ar,

					     ce_ctrl_addr + HOST_IE_ADDRESS);



	ath10k_pci_write32(ar, ce_ctrl_addr + HOST_IE_ADDRESS,

	ar->bus_write32(ar, ce_ctrl_addr + HOST_IE_ADDRESS,

			   host_ie_addr & ~CE_WATERMARK_MASK);

}



static inline void ath10k_ce_error_intr_enable(struct ath10k *ar,

					       u32 ce_ctrl_addr)

{

	u32 misc_ie_addr = ath10k_pci_read32(ar,

	u32 misc_ie_addr = ar->bus_read32(ar,

					     ce_ctrl_addr + MISC_IE_ADDRESS);



	ath10k_pci_write32(ar, ce_ctrl_addr + MISC_IE_ADDRESS,

	ar->bus_write32(ar, ce_ctrl_addr + MISC_IE_ADDRESS,

			   misc_ie_addr | CE_ERROR_MASK);

}



static inline void ath10k_ce_error_intr_disable(struct ath10k *ar,

						u32 ce_ctrl_addr)

{

	u32 misc_ie_addr = ath10k_pci_read32(ar,

	u32 misc_ie_addr = ar->bus_read32(ar,

					     ce_ctrl_addr + MISC_IE_ADDRESS);



	ath10k_pci_write32(ar, ce_ctrl_addr + MISC_IE_ADDRESS,

	ar->bus_write32(ar, ce_ctrl_addr + MISC_IE_ADDRESS,

			   misc_ie_addr & ~CE_ERROR_MASK);

}
@@ -257,7 +256,7 @@ static inline void ath10k_ce_engine_int_status_clear(struct ath10k *ar, 
						     u32 ce_ctrl_addr,

						     unsigned int mask)

{

	ath10k_pci_write32(ar, ce_ctrl_addr + HOST_IS_ADDRESS, mask);

	ar->bus_write32(ar, ce_ctrl_addr + HOST_IS_ADDRESS, mask);

}



/*
@@ -325,11 +324,10 @@ exit: 
void __ath10k_ce_send_revert(struct ath10k_ce_pipe *pipe)

{

	struct ath10k *ar = pipe->ar;

	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);

	struct ath10k_ce_ring *src_ring = pipe->src_ring;

	u32 ctrl_addr = pipe->ctrl_addr;



	lockdep_assert_held(&ar_pci->ce_lock);

	lockdep_assert_held(&ar->ce_lock);



	/*

	 * This function must be called only if there is an incomplete
@@ -357,13 +355,12 @@ int ath10k_ce_send(struct ath10k_ce_pipe *ce_state, 
		   unsigned int flags)

{

	struct ath10k *ar = ce_state->ar;

	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);

	int ret;



	spin_lock_bh(&ar_pci->ce_lock);

	spin_lock_bh(&ar->ce_lock);

	ret = ath10k_ce_send_nolock(ce_state, per_transfer_context,

				    buffer, nbytes, transfer_id, flags);

	spin_unlock_bh(&ar_pci->ce_lock);

	spin_unlock_bh(&ar->ce_lock);



	return ret;

}
@@ -371,14 +368,13 @@ int ath10k_ce_send(struct ath10k_ce_pipe *ce_state, 
int ath10k_ce_num_free_src_entries(struct ath10k_ce_pipe *pipe)

{

	struct ath10k *ar = pipe->ar;

	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);

	int delta;



	spin_lock_bh(&ar_pci->ce_lock);

	spin_lock_bh(&ar->ce_lock);

	delta = CE_RING_DELTA(pipe->src_ring->nentries_mask,

			      pipe->src_ring->write_index,

			      pipe->src_ring->sw_index - 1);

	spin_unlock_bh(&ar_pci->ce_lock);

	spin_unlock_bh(&ar->ce_lock);



	return delta;

}
@@ -386,13 +382,12 @@ int ath10k_ce_num_free_src_entries(struct ath10k_ce_pipe *pipe) 
int __ath10k_ce_rx_num_free_bufs(struct ath10k_ce_pipe *pipe)

{

	struct ath10k *ar = pipe->ar;

	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);

	struct ath10k_ce_ring *dest_ring = pipe->dest_ring;

	unsigned int nentries_mask = dest_ring->nentries_mask;

	unsigned int write_index = dest_ring->write_index;

	unsigned int sw_index = dest_ring->sw_index;



	lockdep_assert_held(&ar_pci->ce_lock);

	lockdep_assert_held(&ar->ce_lock);



	return CE_RING_DELTA(nentries_mask, write_index, sw_index - 1);

}
@@ -400,7 +395,6 @@ int __ath10k_ce_rx_num_free_bufs(struct ath10k_ce_pipe *pipe) 
int __ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx, u32 paddr)

{

	struct ath10k *ar = pipe->ar;

	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);

	struct ath10k_ce_ring *dest_ring = pipe->dest_ring;

	unsigned int nentries_mask = dest_ring->nentries_mask;

	unsigned int write_index = dest_ring->write_index;
@@ -409,7 +403,7 @@ int __ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx, u32 paddr) 
	struct ce_desc *desc = CE_DEST_RING_TO_DESC(base, write_index);

	u32 ctrl_addr = pipe->ctrl_addr;



	lockdep_assert_held(&ar_pci->ce_lock);

	lockdep_assert_held(&ar->ce_lock);



	if ((pipe->id != 5) &&

	    CE_RING_DELTA(nentries_mask, write_index, sw_index - 1) == 0)
@@ -442,12 +436,11 @@ void ath10k_ce_rx_update_write_idx(struct ath10k_ce_pipe *pipe, u32 nentries) 
int ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx, u32 paddr)

{

	struct ath10k *ar = pipe->ar;

	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);

	int ret;



	spin_lock_bh(&ar_pci->ce_lock);

	spin_lock_bh(&ar->ce_lock);

	ret = __ath10k_ce_rx_post_buf(pipe, ctx, paddr);

	spin_unlock_bh(&ar_pci->ce_lock);

	spin_unlock_bh(&ar->ce_lock);



	return ret;

}
@@ -510,14 +503,13 @@ int ath10k_ce_completed_recv_next(struct ath10k_ce_pipe *ce_state, 
				  unsigned int *nbytesp)

{

	struct ath10k *ar = ce_state->ar;

	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);

	int ret;



	spin_lock_bh(&ar_pci->ce_lock);

	spin_lock_bh(&ar->ce_lock);

	ret = ath10k_ce_completed_recv_next_nolock(ce_state,

						   per_transfer_contextp,

						   nbytesp);

	spin_unlock_bh(&ar_pci->ce_lock);

	spin_unlock_bh(&ar->ce_lock);



	return ret;

}
@@ -532,7 +524,6 @@ int ath10k_ce_revoke_recv_next(struct ath10k_ce_pipe *ce_state, 
	unsigned int write_index;

	int ret;

	struct ath10k *ar;

	struct ath10k_pci *ar_pci;



	dest_ring = ce_state->dest_ring;
@@ -540,9 +531,8 @@ int ath10k_ce_revoke_recv_next(struct ath10k_ce_pipe *ce_state, 
		return -EIO;



	ar = ce_state->ar;

	ar_pci = ath10k_pci_priv(ar);



	spin_lock_bh(&ar_pci->ce_lock);

	spin_lock_bh(&ar->ce_lock);



	nentries_mask = dest_ring->nentries_mask;

	sw_index = dest_ring->sw_index;
@@ -570,7 +560,7 @@ int ath10k_ce_revoke_recv_next(struct ath10k_ce_pipe *ce_state, 
		ret = -EIO;

	}



	spin_unlock_bh(&ar_pci->ce_lock);

	spin_unlock_bh(&ar->ce_lock);



	return ret;

}
@@ -638,7 +628,6 @@ int ath10k_ce_cancel_send_next(struct ath10k_ce_pipe *ce_state, 
	unsigned int write_index;

	int ret;

	struct ath10k *ar;

	struct ath10k_pci *ar_pci;



	src_ring = ce_state->src_ring;
@@ -646,9 +635,8 @@ int ath10k_ce_cancel_send_next(struct ath10k_ce_pipe *ce_state, 
		return -EIO;



	ar = ce_state->ar;

	ar_pci = ath10k_pci_priv(ar);



	spin_lock_bh(&ar_pci->ce_lock);

	spin_lock_bh(&ar->ce_lock);



	nentries_mask = src_ring->nentries_mask;

	sw_index = src_ring->sw_index;
@@ -679,7 +667,7 @@ int ath10k_ce_cancel_send_next(struct ath10k_ce_pipe *ce_state, 
		ret = -EIO;

	}



	spin_unlock_bh(&ar_pci->ce_lock);

	spin_unlock_bh(&ar->ce_lock);



	return ret;

}
@@ -688,13 +676,12 @@ int ath10k_ce_completed_send_next(struct ath10k_ce_pipe *ce_state, 
				  void **per_transfer_contextp)

{

	struct ath10k *ar = ce_state->ar;

	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);

	int ret;



	spin_lock_bh(&ar_pci->ce_lock);

	spin_lock_bh(&ar->ce_lock);

	ret = ath10k_ce_completed_send_next_nolock(ce_state,

						   per_transfer_contextp);

	spin_unlock_bh(&ar_pci->ce_lock);

	spin_unlock_bh(&ar->ce_lock);



	return ret;

}
@@ -707,17 +694,17 @@ int ath10k_ce_completed_send_next(struct ath10k_ce_pipe *ce_state, 
 */

void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id)

{

	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);

	struct ath10k_ce_pipe *ce_state = &ar_pci->ce_states[ce_id];

	struct ath10k_ce_pipe *ce_state =

			((struct ath10k_ce_pipe *)ar->ce_states + ce_id);

	u32 ctrl_addr = ce_state->ctrl_addr;



	spin_lock_bh(&ar_pci->ce_lock);

	spin_lock_bh(&ar->ce_lock);



	/* Clear the copy-complete interrupts that will be handled here. */

	ath10k_ce_engine_int_status_clear(ar, ctrl_addr,

					  HOST_IS_COPY_COMPLETE_MASK);



	spin_unlock_bh(&ar_pci->ce_lock);

	spin_unlock_bh(&ar->ce_lock);



	if (ce_state->recv_cb)

		ce_state->recv_cb(ce_state);
@@ -725,7 +712,7 @@ void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id) 
	if (ce_state->send_cb)

		ce_state->send_cb(ce_state);



	spin_lock_bh(&ar_pci->ce_lock);

	spin_lock_bh(&ar->ce_lock);



	/*

	 * Misc CE interrupts are not being handled, but still need
@@ -733,7 +720,7 @@ void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id) 
	 */

	ath10k_ce_engine_int_status_clear(ar, ctrl_addr, CE_WATERMARK_MASK);



	spin_unlock_bh(&ar_pci->ce_lock);

	spin_unlock_bh(&ar->ce_lock);

}



/*
@@ -799,22 +786,22 @@ int ath10k_ce_disable_interrupts(struct ath10k *ar) 


void ath10k_ce_enable_interrupts(struct ath10k *ar)

{

	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);

	int ce_id;



	/* Skip the last copy engine, CE7 the diagnostic window, as that

	 * uses polling and isn't initialized for interrupts.

	 */

	for (ce_id = 0; ce_id < CE_COUNT - 1; ce_id++)

		ath10k_ce_per_engine_handler_adjust(&ar_pci->ce_states[ce_id]);

		ath10k_ce_per_engine_handler_adjust(

			((struct ath10k_ce_pipe *)ar->ce_states + ce_id));

}



static int ath10k_ce_init_src_ring(struct ath10k *ar,

				   unsigned int ce_id,

				   const struct ce_attr *attr)

{

	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);

	struct ath10k_ce_pipe *ce_state = &ar_pci->ce_states[ce_id];

	struct ath10k_ce_pipe *ce_state =

			((struct ath10k_ce_pipe *)ar->ce_states + ce_id);

	struct ath10k_ce_ring *src_ring = ce_state->src_ring;

	u32 nentries, ctrl_addr = ath10k_ce_base_address(ar, ce_id);
@@ -850,8 +837,8 @@ static int ath10k_ce_init_dest_ring(struct ath10k *ar, 
				    unsigned int ce_id,

				    const struct ce_attr *attr)

{

	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);

	struct ath10k_ce_pipe *ce_state = &ar_pci->ce_states[ce_id];

	struct ath10k_ce_pipe *ce_state =

			((struct ath10k_ce_pipe *)ar->ce_states + ce_id);

	struct ath10k_ce_ring *dest_ring = ce_state->dest_ring;

	u32 nentries, ctrl_addr = ath10k_ce_base_address(ar, ce_id);
@@ -1040,8 +1027,8 @@ void ath10k_ce_deinit_pipe(struct ath10k *ar, unsigned int ce_id) 
int ath10k_ce_alloc_pipe(struct ath10k *ar, int ce_id,

			 const struct ce_attr *attr)

{

	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);

	struct ath10k_ce_pipe *ce_state = &ar_pci->ce_states[ce_id];

	struct ath10k_ce_pipe *ce_state =

			((struct ath10k_ce_pipe *)ar->ce_states + ce_id);

	int ret;



	/*
@@ -1097,8 +1084,8 @@ int ath10k_ce_alloc_pipe(struct ath10k *ar, int ce_id, 


void ath10k_ce_free_pipe(struct ath10k *ar, int ce_id)

{

	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);

	struct ath10k_ce_pipe *ce_state = &ar_pci->ce_states[ce_id];

	struct ath10k_ce_pipe *ce_state =

			((struct ath10k_ce_pipe *)ar->ce_states + ce_id);



	if (ce_state->src_ring) {

		dma_free_coherent(ar->dev,

drivers/net/wireless/ath/ath10k/ce.h

+1 −1
Original line number Diff line number Diff line
@@ -425,7 +425,7 @@ static inline u32 ath10k_ce_base_address(struct ath10k *ar, unsigned int ce_id) 


#define CE_INTERRUPT_SUMMARY(ar) \

	CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET( \

		ath10k_pci_read32((ar), CE_WRAPPER_BASE_ADDRESS + \

		ar->bus_read32((ar), CE_WRAPPER_BASE_ADDRESS + \

		CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS))



#endif /* _CE_H_ */

drivers/net/wireless/ath/ath10k/core.h

+4 −0
Original line number Diff line number Diff line
@@ -912,6 +912,10 @@ struct ath10k { 
	struct net_device napi_dev;

	struct napi_struct napi;



	void (*bus_write32)(void *ar, u32 offset, u32 value);

	u32 (*bus_read32)(void *ar, u32 offset);

	spinlock_t ce_lock; /* lock for CE access */

	void *ce_states;

	/* must be last */

	u8 drv_priv[0] __aligned(sizeof(void *));

};

drivers/net/wireless/ath/ath10k/hif.h

+2 −2
Original line number Diff line number Diff line
@@ -74,9 +74,9 @@ struct ath10k_hif_ops { 


	u16 (*get_free_queue_number)(struct ath10k *ar, u8 pipe_id);



	u32 (*read32)(struct ath10k *ar, u32 address);

	u32 (*read32)(void *ar, u32 address);



	void (*write32)(struct ath10k *ar, u32 address, u32 value);

	void (*write32)(void *ar, u32 address, u32 value);



	/* Power up the device and enter BMI transfer mode for FW download */

	int (*power_up)(struct ath10k *ar);

drivers/net/wireless/ath/ath10k/pci.c

+12 −2
Original line number Diff line number Diff line
@@ -669,14 +669,14 @@ static u32 ath10k_bus_pci_read32(struct ath10k *ar, u32 offset) 
	return val;

}



inline void ath10k_pci_write32(struct ath10k *ar, u32 offset, u32 value)

inline void ath10k_pci_write32(void *ar, u32 offset, u32 value)

{

	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);



	ar_pci->bus_ops->write32(ar, offset, value);

}



inline u32 ath10k_pci_read32(struct ath10k *ar, u32 offset)

inline u32 ath10k_pci_read32(void *ar, u32 offset)

{

	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
@@ -3246,6 +3246,16 @@ static int ath10k_pci_probe(struct pci_dev *pdev, 
	ar->id.subsystem_vendor = pdev->subsystem_vendor;

	ar->id.subsystem_device = pdev->subsystem_device;



	spin_lock_init(&ar_pci->ce_lock);

	spin_lock_init(&ar_pci->ps_lock);



	ar->bus_write32 = ath10k_pci_write32;

	ar->bus_read32 = ath10k_pci_read32;

	ar->ce_lock = ar_pci->ce_lock;

	ar->ce_states = ar_pci->ce_states;



	setup_timer(&ar_pci->rx_post_retry, ath10k_pci_rx_replenish_retry,

		    (unsigned long)ar);

	setup_timer(&ar_pci->ps_timer, ath10k_pci_ps_timer,

		    (unsigned long)ar);