Loading arch/arm/boot/dts/qcom/msmcobalt-coresight.dtsi +9 −1 Original line number Diff line number Diff line Loading @@ -39,10 +39,18 @@ }; replicator: replicator@6046000 { compatible = "arm,coresight-replicator"; compatible = "arm,primecell"; arm,primecell-periphid = <0x0003b909>; reg = <0x6046000 0x1000>; reg-names = "replicator-base"; coresight-name = "coresight-replicator"; clocks = <&clock_gcc clk_qdss_clk>, <&clock_gcc clk_qdss_a_clk>; clock-names = "apb_pclk", "core_a_clk"; ports{ #address-cells = <1>; #size-cells = <0>; Loading Loading
arch/arm/boot/dts/qcom/msmcobalt-coresight.dtsi +9 −1 Original line number Diff line number Diff line Loading @@ -39,10 +39,18 @@ }; replicator: replicator@6046000 { compatible = "arm,coresight-replicator"; compatible = "arm,primecell"; arm,primecell-periphid = <0x0003b909>; reg = <0x6046000 0x1000>; reg-names = "replicator-base"; coresight-name = "coresight-replicator"; clocks = <&clock_gcc clk_qdss_clk>, <&clock_gcc clk_qdss_a_clk>; clock-names = "apb_pclk", "core_a_clk"; ports{ #address-cells = <1>; #size-cells = <0>; Loading