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Commit fd5e62e2 authored by Sergei Shtylyov's avatar Sergei Shtylyov Committed by Jeff Garzik
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pata_hpt{37x|3x2n}: improve timing register documentation 



Describe UDMA timing bits 18-20 and 21 separately; add a note to bit
31 about it being meaningful for PIO only.  Reformat the whole comment,
while at it...

Signed-off-by: default avatarSergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: default avatarJeff Garzik <jgarzik@redhat.com>
parent 859faa87

drivers/ata/pata_hpt37x.c

+15 −16
Original line number Diff line number Diff line
@@ -39,25 +39,24 @@ struct hpt_chip { 


/* key for bus clock timings

 * bit

 * 0:3    data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW

 *        DMA. cycles = value + 1

 * 4:8    data_low_time. active time of DIOW_/DIOR_ for PIO and MW

 *        DMA. cycles = value + 1

 * 9:12   cmd_high_time. inactive time of DIOW_/DIOR_ during task file

 * 0:3    data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.

 *        cycles = value + 1

 * 4:8    data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.

 *        cycles = value + 1

 * 9:12   cmd_high_time. Inactive time of DIOW_/DIOR_ during task file

 *        register access.

 * 13:17  cmd_low_time. active time of DIOW_/DIOR_ during task file

 * 13:17  cmd_low_time. Active time of DIOW_/DIOR_ during task file

 *        register access.

 * 18:21  udma_cycle_time. clock freq and clock cycles for UDMA xfer.

 *        during task file register access.

 * 22:24  pre_high_time. time to initialize 1st cycle for PIO and MW DMA

 *        xfer.

 * 25:27  cmd_pre_high_time. time to initialize 1st PIO cycle for task

 * 18:20  udma_cycle_time. Clock cycles for UDMA xfer.

 * 21     CLK frequency for UDMA: 0=ATA clock, 1=dual ATA clock.

 * 22:24  pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer.

 * 25:27  cmd_pre_high_time. Time to initialize 1st PIO cycle for task file

 *        register access.

 * 28     UDMA enable

 * 29     DMA enable

 * 30     PIO_MST enable. if set, the chip is in bus master mode during

 *        PIO.

 * 31     FIFO enable.

 * 28     UDMA enable.

 * 29     DMA  enable.

 * 30     PIO_MST enable. If set, the chip is in bus master mode during

 *        PIO xfer.

 * 31     FIFO enable. Only for PIO.

 */



static struct hpt_clock hpt37x_timings_33[] = {

drivers/ata/pata_hpt3x2n.c

+15 −16
Original line number Diff line number Diff line
@@ -45,25 +45,24 @@ struct hpt_chip { 


/* key for bus clock timings

 * bit

 * 0:3    data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW

 *        DMA. cycles = value + 1

 * 4:8    data_low_time. active time of DIOW_/DIOR_ for PIO and MW

 *        DMA. cycles = value + 1

 * 9:12   cmd_high_time. inactive time of DIOW_/DIOR_ during task file

 * 0:3    data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.

 *        cycles = value + 1

 * 4:8    data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.

 *        cycles = value + 1

 * 9:12   cmd_high_time. Inactive time of DIOW_/DIOR_ during task file

 *        register access.

 * 13:17  cmd_low_time. active time of DIOW_/DIOR_ during task file

 * 13:17  cmd_low_time. Active time of DIOW_/DIOR_ during task file

 *        register access.

 * 18:21  udma_cycle_time. clock freq and clock cycles for UDMA xfer.

 *        during task file register access.

 * 22:24  pre_high_time. time to initialize 1st cycle for PIO and MW DMA

 *        xfer.

 * 25:27  cmd_pre_high_time. time to initialize 1st PIO cycle for task

 * 18:20  udma_cycle_time. Clock cycles for UDMA xfer.

 * 21     CLK frequency for UDMA: 0=ATA clock, 1=dual ATA clock.

 * 22:24  pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer.

 * 25:27  cmd_pre_high_time. Time to initialize 1st PIO cycle for task file

 *        register access.

 * 28     UDMA enable

 * 29     DMA enable

 * 30     PIO_MST enable. if set, the chip is in bus master mode during

 *        PIO.

 * 31     FIFO enable.

 * 28     UDMA enable.

 * 29     DMA  enable.

 * 30     PIO_MST enable. If set, the chip is in bus master mode during

 *        PIO xfer.

 * 31     FIFO enable. Only for PIO.

 */



/* 66MHz DPLL clocks */