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Commit fa501262 authored by Shubhraprakash Das's avatar Shubhraprakash Das
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ARM: dts: msm: camera: Use correct clock on msmcobalt 



Use mmssnoc_axi clk instead of maxi_clk. Only, mmssnoc_axi
clock is needed to satisfy the camera clock dependencies.

CRs-Fixed: 1066418
Change-Id: I92b8ff43f3b4604bba43aa1eb1ea110863bd12a7
Signed-off-by: default avatarShubhraprakash Das <sadas@codeaurora.org>
parent cb4d23d6

arch/arm/boot/dts/qcom/msmcobalt-camera.dtsi

+10 −11
Original line number Diff line number Diff line
@@ -320,7 +320,7 @@ 
		camss-vdd-supply = <&gdsc_camss_top>;

		vdd-supply = <&gdsc_cpp>;

		qcom,vdd-names = "smmu-vdd", "camss-vdd", "vdd";

		clocks = <&clock_mmss clk_mmss_mnoc_maxi_clk>,

		clocks = <&clock_gcc clk_mmssnoc_axi_clk>,

			<&clock_mmss clk_mmss_mnoc_ahb_clk>,

			<&clock_mmss clk_mmss_bimc_smmu_ahb_clk>,

			<&clock_mmss clk_mmss_bimc_smmu_axi_clk>,
@@ -331,7 +331,7 @@ 
			<&clock_mmss clk_mmss_fd_ahb_clk>,

			<&clock_mmss clk_mmss_camss_cpp_axi_clk>,

			<&clock_mmss clk_mmss_camss_cpp_vbif_ahb_clk>;

		clock-names = "mmss_mnoc_maxi_clk",

		clock-names = "mmssnoc_axi",

			"mmss_mnoc_ahb_clk",

			"mmss_bimc_smmu_ahb_clk",

			"mmss_bimc_smmu_axi_clk",
@@ -374,7 +374,6 @@ 
		vdd-supply = <&gdsc_cpp>;

		qcom,vdd-names = "smmu-vdd", "camss-vdd", "vdd";

		clocks = <&clock_gcc clk_mmssnoc_axi_clk>,

			<&clock_mmss clk_mmss_mnoc_maxi_clk>,

			<&clock_mmss clk_mmss_mnoc_ahb_clk>,

			<&clock_mmss clk_mmss_camss_ahb_clk>,

			<&clock_mmss clk_mmss_camss_top_ahb_clk>,
@@ -385,12 +384,12 @@ 
			<&clock_mmss clk_mmss_bimc_smmu_axi_clk>,

			<&clock_mmss clk_mmss_camss_cpp_vbif_ahb_clk>;

		clock-names = "mmssnoc_axi_clk",

			"mnoc_maxi_clk", "mnoc_ahb_clk",

			"mnoc_ahb_clk",

			"camss_ahb_clk", "camss_top_ahb_clk",

			"cpp_core_clk", "camss_cpp_ahb_clk",

			"camss_cpp_axi_clk", "micro_iface_clk",

			"mmss_smmu_axi_clk", "cpp_vbif_ahb_clk";

		qcom,clock-rates = <0 0 0 0 0 200000000 0 0 0 0 0>;

		qcom,clock-rates = <0 0 0 0 200000000 0 0 0 0 0>;

		qcom,min-clock-rate = <200000000>;

		qcom,bus-master = <1>;

		qcom,vbif-qos-setting = <0x20 0x10000000>,
@@ -687,7 +686,7 @@ 
		mmagic-supply = <&gdsc_bimc_smmu>;

		gdscr-supply = <&gdsc_camss_top>;

		qcom,cam-vreg-name = "mmagic", "gdscr";

		clocks = <&clock_mmss clk_mmss_mnoc_maxi_clk>,

		clocks = <&clock_gcc clk_mmssnoc_axi_clk>,

			<&clock_mmss clk_mmss_mnoc_ahb_clk>,

			<&clock_mmss clk_mmss_bimc_smmu_ahb_clk>,

			<&clock_mmss clk_mmss_bimc_smmu_axi_clk>,
@@ -696,7 +695,7 @@ 
			<&clock_mmss clk_cci_clk_src>,

			<&clock_mmss clk_mmss_camss_cci_ahb_clk>,

			<&clock_mmss clk_mmss_camss_cci_clk>;

		clock-names = "mnoc_axi", "mnoc_ahb", "smmu_ahb", "smmu_axi",

		clock-names = "mmssnoc_axi", "mnoc_ahb", "smmu_ahb", "smmu_axi",

			"camss_ahb_clk", "camss_top_ahb_clk",

			"cci_src_clk", "cci_ahb_clk", "camss_cci_clk";

		qcom,clock-rates = <0 0 0 0 0 0 19200000 0 0>,
@@ -739,7 +738,7 @@ 
		smmu-vdd-supply = <&gdsc_bimc_smmu>;

		camss-vdd-supply = <&gdsc_camss_top>;

		qcom,vdd-names = "smmu-vdd", "camss-vdd";

		clock-names = "mmss_mnoc_maxi_clk",

		clock-names = "mmssnoc_axi",

			"mmss_mnoc_ahb_clk",

			"mmss_bimc_smmu_ahb_clk",

			"mmss_bimc_smmu_axi_clk",
@@ -748,7 +747,7 @@ 
			"core_clk",

			"mmss_camss_jpeg_ahb_clk",

			"mmss_camss_jpeg_axi_clk";

		clocks = <&clock_mmss clk_mmss_mnoc_maxi_clk>,

		clocks = <&clock_gcc clk_mmssnoc_axi_clk>,

			<&clock_mmss clk_mmss_mnoc_ahb_clk>,

			<&clock_mmss clk_mmss_bimc_smmu_ahb_clk>,

			<&clock_mmss clk_mmss_bimc_smmu_axi_clk>,
@@ -783,7 +782,7 @@ 
		smmu-vdd-supply = <&gdsc_bimc_smmu>;

		camss-vdd-supply = <&gdsc_camss_top>;

		qcom,vdd-names = "smmu-vdd", "camss-vdd";

		clock-names = "mmss_mnoc_maxi_clk",

		clock-names = "mmssnoc_axi",

			"mmss_mnoc_ahb_clk",

			"mmss_bimc_smmu_ahb_clk",

			"mmss_bimc_smmu_axi_clk",
@@ -792,7 +791,7 @@ 
			"core_clk",

			"mmss_camss_jpeg_ahb_clk",

			"mmss_camss_jpeg_axi_clk";

		clocks = <&clock_mmss clk_mmss_mnoc_maxi_clk>,

		clocks = <&clock_gcc clk_mmssnoc_axi_clk>,

			<&clock_mmss clk_mmss_mnoc_ahb_clk>,

			<&clock_mmss clk_mmss_bimc_smmu_ahb_clk>,

			<&clock_mmss clk_mmss_bimc_smmu_axi_clk>,