Promotion of kernel.lnx.4.4-160615.

- APQTITANIUM

  compatible = "qcom,apqtitanium"

- APQCOBALT

  compatible = "qcom,apqcobalt"

- MDM9630

  compatible = "qcom,mdm9630"

compatible = "qcom,apq8037-mtp"

compatible = "qcom,apqtitanium-cdp"

compatible = "qcom,apqtitanium-mtp"

compatible = "qcom,apqcobalt-cdp"

compatible = "qcom,apqcobalt-mtp"

compatible = "qcom,mdm9630-cdp"

compatible = "qcom,mdm9630-mtp"

compatible = "qcom,mdm9630-sim"

compatible = "qcom,msm8996-adp"

compatible = "qcom,msmcobalt-sim"

compatible = "qcom,msmcobalt-rumi"

compatible = "qcom,msmcobalt-qrd"

compatible = "qcom,msmhamster-rumi"

compatible = "qcom,msmhamster-cdp"

compatible = "qcom,msmhamster-mtp"

Qualcomm Technologies, Inc. I2C PMIC Interrupt Controller

Platform Independent Bindings

The I2C PMIC Controller is used by multi-function PMIC devices which communicate

over the I2C bus. An I2C PMIC controller node typically contains one or more

child nodes representing the device's peripherals. Each of the peripherals

typically has its own driver on the platform bus and will be enumerated by this

controller. The controller exposes a regmap to the peripherals to communicate

over the I2C bus.

The controller also controls interrupts for all of the peripherals on the bus.

The controller takes a summary interrupt, deciphers which peripheral triggered

the interrupt, and which of the peripheral's interrupts were triggered. Finally,

it calls the handlers for each of the virtual interrupts that were registered.

This document describes the common platform independent bindings that apply

to all I2C PMIC interrupt controllers.

========================================

First Level Nodes - I2C PMIC Controllers

========================================

Platform independent properties:

- compatible

	Usage:      required

	Value type: <string>

	Definition: Must be "qcom,i2c-pmic".

- reg

	Usage:      required

	Value type: <u32>

	Definition: 7-bit I2C address of the device.

- interrupt-parent

	Usage:      required

	Value type: <phandle>

	Definition: phandle of the interrupt controller which services the

		    summary interrupt.

- interrupts

	Usage:      required

	Value type: <prop-encoded-array>

	Definition: Summary interrupt specifier.

- interrupt-controller

	Usage:      required

	Value type: <empty>

	Definition: Boolean flag which indicates this device node is an

		    interrupt controller.

- #interrupt-cells

	Usage:      required

	Value type: <u32>

	Definition: Number of cells to encode an interrupt source.

- qcom,periph-map

	Usage:      required

	Value type: <prop-encoded-array>

	Definition: A list of u32 arrays. This provides a mapping between the

		    summary status register bits and peripheral addresses.

		    The number of arrays should match the number of summary

		    registers with up to 8 elements each. One element per bit

		    of the summary status register in order from the least

		    sigificant bit to the most significant bit.

- pinctrl-names

	Usage:      optional

	Value type: <string-list>

	Definition: Should be "default".

		    Please refer to pinctrl-bindings.txt

- pinctrl-0

	Usage:      optional

	Value type: <phandle-list>

	Definition: phandle of the pin configuration.

		    Please refer to pinctrl-bindings.txt

=======

Example

=======

&i2c_3 {

	status = "ok";

	qcom,smb138x@8 {

		compatible = "qcom,i2c-pmic";

		reg = <0x8>;

		interrupt-parent = <&tlmm_pinmux>;

		interrupts = <83 0>;

		interrupt-controller;

		#interrupt-cells = <3>;

		pinctrl-names = "default";

		pinctrl-0 = <&smb_stat_active>;

		#address-cells = <1>;

		#size-cells = <0>;

		qcom,periph-map = <0x10 0x11 0x12 0x13 0x14 0x16 0x36>;

	};

};

QPNP Qnovo pulse engine

QPNP Qnovo is a pulse charging engine which works in tandem with the QPNP SMB2

Charger device. It configures the QPNP SMB2 charger to charge/discharge as per

pulse characteristics.

The QPNP Qnovo pulse engine has a single peripheral assigned to it.

Required properties:

- compatible:		Must be "qcom,qpnp-qnovo"

- qcom,pmic-revid:	Should specify the phandle of PMIC

			revid module. This is used to identify

			the PMIC subtype.

- reg:			The address for this peripheral

- interrupts:		Specifies the interrupt associated with the peripheral.

- interrupt-names:	Specifies the interrupt name for the peripheral. Qnovo

			peripheral has only one interrupt "ptrain-done".

Optional Properties:

- qcom,external-rsense:		To indicate whether the platform uses external or

				internal rsense for measuring battery current.

Example:

	qcom,qpnp-qnovo@1500 {

		compatible = "qcom,qpnp-qnovo";

		reg = <0x1500 0x100>;

		interrupts = <0x2 0x15 0x0 IRQ_TYPE_NONE>;

		interrupt-names = "ptrain-done";

		qcom,pmic-revid = <&pmicobalt_revid>;

	};

	help

	  Support for Intel/Marvell's PXA2xx/PXA3xx processor line.

config ARCH_QCOM

	bool "Qualcomm MSM (non-multiplatform)"

	select ARCH_REQUIRE_GPIOLIB

	select CPU_V7

	select AUTO_ZRELADDR

	select HAVE_SMP

	select CLKDEV_LOOKUP

	select GENERIC_CLOCKEVENTS

	select GENERIC_ALLOCATOR

	select ARM_PATCH_PHYS_VIRT

	select ARM_HAS_SG_CHAIN

	select ARCH_HAS_OPP

	select SOC_BUS

	select MULTI_IRQ_HANDLER

	select PM_OPP

	select SPARSE_IRQ

	select USE_OF

	select PINCTRL

	help

	  Support for Qualcomm MSM/QSD based systems.  This runs on the

	  apps processor of the MSM/QSD and depends on a shared memory

	  interface to the modem processor which runs the baseband

	  stack and controls some vital subsystems

	  (clock and power control, etc).

config ARCH_RPC

	bool "RiscPC"

	depends on MMU

config ARCH_NR_GPIO

	int

	default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \

		ARCH_ZYNQ

		ARCH_ZYNQ || ARCH_QCOM

	default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \

		SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210

	default 416 if ARCH_SUNXI

config UNCOMPRESS_INCLUDE

	string

	default "debug/uncompress.h" if ARCH_MULTIPLATFORM || ARCH_MSM || \

					PLAT_SAMSUNG || ARM_SINGLE_ARMV7M

				ARCH_QCOM || PLAT_SAMSUNG || ARM_SINGLE_ARMV7M

	default "mach/uncompress.h"

config EARLY_PRINTK