Merge "ARM: dts: msm: add support for qdss nodes on msmfalcon" (f9d64cd4) · Commits · e / devices / android_kernel_sony_msm8998

arch/arm/boot/dts/qcom/msmfalcon-coresight.dtsi

+302 −0

Original line number	Diff line number	Diff line
		@@ -26,6 +26,8 @@
		arm,buffer-size = <0x400000>;
		arm,sg-enable;

		coresight-ctis = <&cti0 &cti8>;

		coresight-name = "coresight-tmc-etr";

		clocks = <&clock_gcc RPM_QDSS_CLK>,
		@@ -76,6 +78,8 @@

		coresight-name = "coresight-tmc-etf";

		coresight-ctis = <&cti0 &cti8>;

		clocks = <&clock_gcc RPM_QDSS_CLK>,
		<&clock_gcc RPM_QDSS_A_CLK>;
		clock-names = "apb_pclk", "core_a_clk";
		@@ -161,6 +165,14 @@
		<&funnel_merg_in_funnel_in0>;
		};
		};
		port@3 {
		reg = <6>;
		funnel_in0_in_funnel_qatb: endpoint {
		slave-mode;
		remote-endpoint =
		<&funnel_qatb_out_funnel_in0>;
		};
		};
		port@4 {
		reg = <7>;
		funnel_in0_in_stm: endpoint {
		@@ -191,4 +203,294 @@
		};
		};
		};

		cti0: cti@6010000 {
		compatible = "arm,coresight-cti";
		reg = <0x6010000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti0";

		clocks = <&clock_gcc RPM_QDSS_CLK>,
		<&clock_gcc RPM_QDSS_A_CLK>;
		clock-names = "core_clk", "core_a_clk";
		};

		cti1: cti@6011000 {
		compatible = "arm,coresight-cti";
		reg = <0x6011000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti1";

		clocks = <&clock_gcc RPM_QDSS_CLK>,
		<&clock_gcc RPM_QDSS_A_CLK>;
		clock-names = "core_clk", "core_a_clk";
		};

		cti2: cti@6012000 {
		compatible = "arm,coresight-cti";
		reg = <0x6012000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti2";

		clocks = <&clock_gcc RPM_QDSS_CLK>,
		<&clock_gcc RPM_QDSS_A_CLK>;
		clock-names = "core_clk", "core_a_clk";
		};

		cti3: cti@6013000 {
		compatible = "arm,coresight-cti";
		reg = <0x6013000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti3";

		clocks = <&clock_gcc RPM_QDSS_CLK>,
		<&clock_gcc RPM_QDSS_A_CLK>;
		clock-names = "core_clk", "core_a_clk";
		};

		cti4: cti@6014000 {
		compatible = "arm,coresight-cti";
		reg = <0x6014000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti4";

		clocks = <&clock_gcc RPM_QDSS_CLK>,
		<&clock_gcc RPM_QDSS_A_CLK>;
		clock-names = "core_clk", "core_a_clk";
		};

		cti5: cti@6015000 {
		compatible = "arm,coresight-cti";
		reg = <0x6015000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti5";

		clocks = <&clock_gcc RPM_QDSS_CLK>,
		<&clock_gcc RPM_QDSS_A_CLK>;
		clock-names = "core_clk", "core_a_clk";
		};

		cti6: cti@6016000 {
		compatible = "arm,coresight-cti";
		reg = <0x6016000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti6";

		clocks = <&clock_gcc RPM_QDSS_CLK>,
		<&clock_gcc RPM_QDSS_A_CLK>;
		clock-names = "core_clk", "core_a_clk";
		};

		cti7: cti@6017000 {
		compatible = "arm,coresight-cti";
		reg = <0x6017000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti7";

		clocks = <&clock_gcc RPM_QDSS_CLK>,
		<&clock_gcc RPM_QDSS_A_CLK>;
		clock-names = "core_clk", "core_a_clk";
		};

		cti8: cti@6018000 {
		compatible = "arm,coresight-cti";
		reg = <0x6018000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti8";

		clocks = <&clock_gcc RPM_QDSS_CLK>,
		<&clock_gcc RPM_QDSS_A_CLK>;
		clock-names = "core_clk", "core_a_clk";
		};

		cti9: cti@6019000 {
		compatible = "arm,coresight-cti";
		reg = <0x6019000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti9";

		clocks = <&clock_gcc RPM_QDSS_CLK>,
		<&clock_gcc RPM_QDSS_A_CLK>;
		clock-names = "core_clk", "core_a_clk";
		};

		cti10: cti@601a000 {
		compatible = "arm,coresight-cti";
		reg = <0x601a000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti10";

		clocks = <&clock_gcc RPM_QDSS_CLK>,
		<&clock_gcc RPM_QDSS_A_CLK>;
		clock-names = "core_clk", "core_a_clk";
		};

		cti11: cti@601b000 {
		compatible = "arm,coresight-cti";
		reg = <0x601b000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti11";

		clocks = <&clock_gcc RPM_QDSS_CLK>,
		<&clock_gcc RPM_QDSS_A_CLK>;
		clock-names = "core_clk", "core_a_clk";
		};

		cti12: cti@601c000 {
		compatible = "arm,coresight-cti";
		reg = <0x601c000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti12";

		clocks = <&clock_gcc RPM_QDSS_CLK>,
		<&clock_gcc RPM_QDSS_A_CLK>;
		clock-names = "core_clk", "core_a_clk";
		};

		cti13: cti@601d000 {
		compatible = "arm,coresight-cti";
		reg = <0x601d000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti13";

		clocks = <&clock_gcc RPM_QDSS_CLK>,
		<&clock_gcc RPM_QDSS_A_CLK>;
		clock-names = "core_clk", "core_a_clk";
		};

		cti14: cti@601e000 {
		compatible = "arm,coresight-cti";
		reg = <0x601e000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti14";

		clocks = <&clock_gcc RPM_QDSS_CLK>,
		<&clock_gcc RPM_QDSS_A_CLK>;
		clock-names = "core_clk", "core_a_clk";
		};

		cti15: cti@601f000 {
		compatible = "arm,coresight-cti";
		reg = <0x601f000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti15";

		clocks = <&clock_gcc RPM_QDSS_CLK>,
		<&clock_gcc RPM_QDSS_A_CLK>;
		clock-names = "core_clk", "core_a_clk";
		};

		funnel_qatb: funnel@6005000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b908>;

		reg = <0x6005000 0x1000>;
		reg-names = "funnel-base";

		coresight-name = "coresight-funnel-qatb";

		clocks = <&clock_gcc RPM_QDSS_CLK>,
		<&clock_gcc RPM_QDSS_A_CLK>;
		clock-names = "apb_pclk", "core_a_clk";

		ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
		reg = <0>;
		funnel_qatb_out_funnel_in0: endpoint {
		remote-endpoint =
		<&funnel_in0_in_funnel_qatb>;
		};
		};
		port@1 {
		reg = <0>;
		funnel_qatb_in_tpda: endpoint {
		slave-mode;
		remote-endpoint =
		<&tpda_out_funnel_qatb>;
		};
		};
		};
		};

		tpda: tpda@6004000 {
		compatible = "qcom,coresight-tpda";
		reg = <0x6004000 0x1000>;
		reg-names = "tpda-base";

		coresight-name = "coresight-tpda";

		qcom,tpda-atid = <65>;
		qcom,bc-elem-size = <7 32>,
		<9 32>;
		qcom,tc-elem-size = <3 32>,
		<6 32>,
		<9 32>;
		qcom,dsb-elem-size = <7 32>,
		<9 32>;
		qcom,cmb-elem-size = <3 32>,
		<4 32>,
		<5 32>,
		<9 64>;

		clocks = <&clock_gcc RPM_QDSS_CLK>,
		<&clock_gcc RPM_QDSS_A_CLK>;
		clock-names = "core_clk", "core_a_clk";

		ports {
		#address-cells = <1>;
		#size-cells = <0>;
		port@0 {
		reg = <0>;
		tpda_out_funnel_qatb: endpoint {
		remote-endpoint =
		<&funnel_qatb_in_tpda>;
		};
		};
		port@2 {
		reg = <5>;
		tpda_in_tpdm_dcc: endpoint {
		slave-mode;
		remote-endpoint =
		<&tpdm_dcc_out_tpda>;
		};
		};
		};
		};

		tpdm_dcc: tpdm@7054000 {
		compatible = "qcom,coresight-tpdm";
		reg = <0x7054000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-dcc";

		clocks = <&clock_gcc RPM_QDSS_CLK>,
		<&clock_gcc RPM_QDSS_A_CLK>;
		clock-names = "core_clk", "core_a_clk";

		port{
		tpdm_dcc_out_tpda: endpoint {
		remote-endpoint = <&tpda_in_tpdm_dcc>;
		};
		};
		};
		};

arch/arm/boot/dts/qcom/msmfalcon.dtsi

+22 −0

Original line number	Diff line number	Diff line
		@@ -252,6 +252,18 @@
		status = "ok";
		};

		wdog: qcom,wdt@17817000 {
		status = "disabled";
		compatible = "qcom,msm-watchdog";
		reg = <0x17817000 0x1000>;
		reg-names = "wdt-base";
		interrupts = <0 3 0>, <0 4 0>;
		qcom,bark-time = <11000>;
		qcom,pet-time = <10000>;
		qcom,ipi-ping;
		qcom,wakeup-enable;
		};

		qcom,sps {
		compatible = "qcom,msm_sps_4k";
		qcom,pipe-attr-ee;
		@@ -380,6 +392,16 @@
		qcom,mpu-enabled;
		};

		dcc: dcc@10b3000 {
		compatible = "qcom,dcc";
		reg = <0x10b3000 0x1000>,
		<0x10b4000 0x800>;
		reg-names = "dcc-base", "dcc-ram-base";

		clocks = <&clock_gcc RPM_QDSS_CLK>;
		clock-names = "dcc_clk";
		};

		qcom,glink-smem-native-xprt-modem@86000000 {
		compatible = "qcom,glink-smem-native-xprt";
		reg = <0x86000000 0x200000>,