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Commit f96e9424 authored by Padmanabhan Komanduru's avatar Padmanabhan Komanduru
Browse files

clk: qcom: mdss: fix the divider programming for DisplayPort PLL 



Fix the divider programming of DisplayPort PLL with the correct
value. Without this, display doesn't up fine with certain
resolutions on some sinks when link rate is 5.4 GHz.

Change-Id: I7c5a452a9df757240a1c6c3d371bd46a16f98efd
Signed-off-by: default avatarPadmanabhan Komanduru <pkomandu@codeaurora.org>
parent b0ba6e47

drivers/clk/msm/mdss/mdss-dp-pll-8998-util.c

+3 −3
Original line number Diff line number Diff line 
/* Copyright (c) 2016, The Linux Foundation. All rights reserved.

/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -128,10 +128,10 @@ int vco_divided_clk_set_div(struct div_clk *clk, int div) 
	auxclk_div = MDSS_PLL_REG_R(dp_res->phy_base, DP_PHY_VCO_DIV);

	auxclk_div &= ~0x03;	/* bits 0 to 1 */



	auxclk_div |= 1; /* Default divider */



	if (div == 4)

		auxclk_div |= 2;

	else

		auxclk_div |= 1; /* Default divider */



	MDSS_PLL_REG_W(dp_res->phy_base,

			DP_PHY_VCO_DIV, auxclk_div);