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Commit f96e9424 authored by Padmanabhan Komanduru's avatar Padmanabhan Komanduru
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clk: qcom: mdss: fix the divider programming for DisplayPort PLL 



Fix the divider programming of DisplayPort PLL with the correct
value. Without this, display doesn't up fine with certain
resolutions on some sinks when link rate is 5.4 GHz.

Change-Id: I7c5a452a9df757240a1c6c3d371bd46a16f98efd
Signed-off-by: default avatarPadmanabhan Komanduru <pkomandu@codeaurora.org>
parent b0ba6e47
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