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Commit f96a299e authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
Browse files

Merge "drm/msm: Add timestamp counter"

parents e28c151a 5c91d852

drivers/gpu/drm/msm/adreno/a3xx_gpu.c

+0 −1
Original line number Diff line number Diff line
@@ -439,7 +439,6 @@ static const struct adreno_gpu_funcs funcs = { 
		.pm_suspend = msm_gpu_pm_suspend,

		.pm_resume = msm_gpu_pm_resume,

		.recover = a3xx_recover,

		.last_fence = adreno_last_fence,

		.submitted_fence = adreno_submitted_fence,

		.submit = adreno_submit,

		.flush = adreno_flush,

drivers/gpu/drm/msm/adreno/a4xx_gpu.c

+0 −1
Original line number Diff line number Diff line
@@ -522,7 +522,6 @@ static const struct adreno_gpu_funcs funcs = { 
		.pm_suspend = a4xx_pm_suspend,

		.pm_resume = a4xx_pm_resume,

		.recover = a4xx_recover,

		.last_fence = adreno_last_fence,

		.submitted_fence = adreno_submitted_fence,

		.submit = adreno_submit,

		.flush = adreno_flush,

drivers/gpu/drm/msm/adreno/a5xx_counters.c

+1 −1
Original line number Diff line number Diff line
@@ -106,7 +106,7 @@ static void a5xx_counter_enable_pm4(struct msm_gpu *gpu, 
{

	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);

	struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);

	struct msm_ringbuffer *ring = gpu->rb[MSM_GPU_MAX_RINGS - 1];

	struct msm_ringbuffer *ring = gpu->rb[0];

	struct adreno_counter *counter = &group->counters[counterid];



	mutex_lock(&gpu->dev->struct_mutex);

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

+8 −3
Original line number Diff line number Diff line
@@ -774,6 +774,9 @@ static int a5xx_hw_init(struct msm_gpu *gpu) 
	gpu_write(gpu, REG_A5XX_TPL1_ADDR_MODE_CNTL, 0x1);

	gpu_write(gpu, REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1);



	a5xx_gpu->timestamp_counter = adreno_get_counter(gpu,

		MSM_COUNTER_GROUP_CP, 0, NULL, NULL);



	/* Load the GPMU firmware before starting the HW init */

	a5xx_gpmu_ucode_init(gpu);
@@ -1218,8 +1221,11 @@ static int a5xx_pm_suspend(struct msm_gpu *gpu) 


static int a5xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value)

{

	*value = gpu_read64(gpu, REG_A5XX_RBBM_PERFCTR_CP_0_LO,

		REG_A5XX_RBBM_PERFCTR_CP_0_HI);

	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);

	struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);



	*value = adreno_read_counter(gpu, MSM_COUNTER_GROUP_CP,

		a5xx_gpu->timestamp_counter);



	return 0;

}
@@ -1252,7 +1258,6 @@ static const struct adreno_gpu_funcs funcs = { 
		.pm_suspend = a5xx_pm_suspend,

		.pm_resume = a5xx_pm_resume,

		.recover = a5xx_recover,

		.last_fence = adreno_last_fence,

		.submitted_fence = adreno_submitted_fence,

		.submit = a5xx_submit,

		.flush = a5xx_flush,

drivers/gpu/drm/msm/adreno/a5xx_gpu.h

+2 −0
Original line number Diff line number Diff line
@@ -56,6 +56,8 @@ struct a5xx_gpu { 
	struct a5xx_smmu_info *smmu_info;

	struct drm_gem_object *smmu_info_bo;

	uint64_t smmu_info_iova;



	int timestamp_counter;

};



#define to_a5xx_gpu(x) container_of(x, struct a5xx_gpu, base)