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Commit f93eaffc authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

iwlegacy: Use standard #defines for PCIe Capability ASPM fields



Use the standard #defines rather than creating local definitions for
PCIe Capability ASPM fields.

Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Acked-by: default avatarStanislaw Gruszka <sgruszka@redhat.com>
parent 94e15613
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+0 −4
Original line number Diff line number Diff line
@@ -917,10 +917,6 @@ struct il4965_scd_bc_tbl {
/* PCI registers */
#define PCI_CFG_RETRY_TIMEOUT	0x041

/* PCI register values */
#define PCI_CFG_LINK_CTRL_VAL_L0S_EN	0x01
#define PCI_CFG_LINK_CTRL_VAL_L1_EN	0x02

#define IL4965_DEFAULT_TX_RETRY  15

/* EEPROM */
+2 −3
Original line number Diff line number Diff line
@@ -1186,7 +1186,7 @@ il_power_initialize(struct il_priv *il)
	u16 lctl;

	pcie_capability_read_word(il->pci_dev, PCI_EXP_LNKCTL, &lctl);
	il->power_data.pci_pm = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
	il->power_data.pci_pm = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);

	il->power_data.debug_sleep_level_override = -1;

@@ -4235,8 +4235,7 @@ il_apm_init(struct il_priv *il)
	 */
	if (il->cfg->set_l0s) {
		pcie_capability_read_word(il->pci_dev, PCI_EXP_LNKCTL, &lctl);
		if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
		    PCI_CFG_LINK_CTRL_VAL_L1_EN) {
		if (lctl & PCI_EXP_LNKCTL_ASPM_L1) {
			/* L1-ASPM enabled; disable(!) L0S  */
			il_set_bit(il, CSR_GIO_REG,
				   CSR_GIO_REG_VAL_L0S_ENABLED);
+0 −4
Original line number Diff line number Diff line
@@ -2426,10 +2426,6 @@ struct il_tfd {
/* PCI registers */
#define PCI_CFG_RETRY_TIMEOUT	0x041

/* PCI register values */
#define PCI_CFG_LINK_CTRL_VAL_L0S_EN	0x01
#define PCI_CFG_LINK_CTRL_VAL_L1_EN	0x02

struct il_rate_info {
	u8 plcp;		/* uCode API:  RATE_6M_PLCP, etc. */
	u8 plcp_siso;		/* uCode API:  RATE_SISO_6M_PLCP, etc. */