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Commit f926204b authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'dsa-next' 



Andrew Lunn says:

====================
More Marvell DSA refactring and fixup

This patch setup continues the refactoring and cleanup of the Marvell
DSA drivers.

Patch #1 Centralizes the duplicated parts of port setup and global
setup into the shared mv88e6xxx.

Patch #2 Centralizes looping over the ports setting them up

Patch #3 Uses mnemonics for the remaining register access in the
drivers.

Patch #4 The 6172 is actually a member of the 6352 family. This moves
the probe code into the correct driver.

Patch #5 Adds more members of the 6171 family to the 6171 driver. The
new devices are untested.

Patch #6 The 6185 is a member of the 6131 family. Add it to the probe
code of the 6131 driver.

Patch #7 and Patch #8 Simply the mutex's in mv88e6xxx.c. The SMI bus
is the bottleneck, not the granularity of the mutex's so simply the
code down to a single mutex.

Patch #8 Fixes a false positive lockdep splat, due to nested uses of
MDIO busses.

Patch #9 Fixes another false positive lockdep splat with the transmit
queue because of stacked Ethernet devices.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 239fb791 448b4482

drivers/net/dsa/Kconfig

+6 −6
Original line number Diff line number Diff line
@@ -37,22 +37,22 @@ config NET_DSA_MV88E6123_61_65 
	  ethernet switch chips.



config NET_DSA_MV88E6171

	tristate "Marvell 88E6171/6172 ethernet switch chip support"

	tristate "Marvell 88E6171/6175/6350/6351 ethernet switch chip support"

	depends on NET_DSA

	select NET_DSA_MV88E6XXX

	select NET_DSA_TAG_EDSA

	---help---

	  This enables support for the Marvell 88E6171/6172 ethernet switch

	  chips.

	  This enables support for the Marvell 88E6171/6175/6350/6351

	  ethernet switches chips.



config NET_DSA_MV88E6352

	tristate "Marvell 88E6176/88E6352 ethernet switch chip support"

	tristate "Marvell 88E6172/88E6176/88E6352 ethernet switch chip support"

	depends on NET_DSA

	select NET_DSA_MV88E6XXX

	select NET_DSA_TAG_EDSA

	---help---

	  This enables support for the Marvell 88E6176 and 88E6352 ethernet

	  switch chips.

	  This enables support for the Marvell 88E6172, 88E6176 and 88E6352

	  ethernet switch chips.



config NET_DSA_BCM_SF2

	tristate "Broadcom Starfighter 2 Ethernet switch support"

drivers/net/dsa/mv88e6123_61_65.c

+13 −173
Original line number Diff line number Diff line
@@ -54,192 +54,40 @@ static char *mv88e6123_61_65_probe(struct device *host_dev, int sw_addr) 


static int mv88e6123_61_65_setup_global(struct dsa_switch *ds)

{

	u32 upstream_port = dsa_upstream_port(ds);

	int ret;

	int i;

	u32 reg;



	ret = mv88e6xxx_setup_global(ds);

	if (ret)

		return ret;



	/* Disable the PHY polling unit (since there won't be any

	 * external PHYs to poll), don't discard packets with

	 * excessive collisions, and mask all interrupt sources.

	 */

	REG_WRITE(REG_GLOBAL, 0x04, 0x0000);



	/* Set the default address aging time to 5 minutes, and

	 * enable address learn messages to be sent to all message

	 * ports.

	 */

	REG_WRITE(REG_GLOBAL, 0x0a, 0x0148);



	/* Configure the priority mapping registers. */

	ret = mv88e6xxx_config_prio(ds);

	if (ret < 0)

		return ret;

	REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, 0x0000);



	/* Configure the upstream port, and configure the upstream

	 * port as the port to which ingress and egress monitor frames

	 * are to be sent.

	 */

	REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1110));

	reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |

		upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT |

		upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT;

	REG_WRITE(REG_GLOBAL, GLOBAL_MONITOR_CONTROL, reg);



	/* Disable remote management for now, and set the switch's

	 * DSA device number.

	 */

	REG_WRITE(REG_GLOBAL, 0x1c, ds->index & 0x1f);



	/* Send all frames with destination addresses matching

	 * 01:80:c2:00:00:2x to the CPU port.

	 */

	REG_WRITE(REG_GLOBAL2, 0x02, 0xffff);



	/* Send all frames with destination addresses matching

	 * 01:80:c2:00:00:0x to the CPU port.

	 */

	REG_WRITE(REG_GLOBAL2, 0x03, 0xffff);



	/* Disable the loopback filter, disable flow control

	 * messages, disable flood broadcast override, disable

	 * removing of provider tags, disable ATU age violation

	 * interrupts, disable tag flow control, force flow

	 * control priority to the highest, and send all special

	 * multicast frames to the CPU at the highest priority.

	 */

	REG_WRITE(REG_GLOBAL2, 0x05, 0x00ff);



	/* Program the DSA routing table. */

	for (i = 0; i < 32; i++) {

		int nexthop;



		nexthop = 0x1f;

		if (i != ds->index && i < ds->dst->pd->nr_chips)

			nexthop = ds->pd->rtable[i] & 0x1f;



		REG_WRITE(REG_GLOBAL2, 0x06, 0x8000 | (i << 8) | nexthop);

	}



	/* Clear all trunk masks. */

	for (i = 0; i < 8; i++)

		REG_WRITE(REG_GLOBAL2, 0x07, 0x8000 | (i << 12) | 0xff);



	/* Clear all trunk mappings. */

	for (i = 0; i < 16; i++)

		REG_WRITE(REG_GLOBAL2, 0x08, 0x8000 | (i << 11));



	/* Disable ingress rate limiting by resetting all ingress

	 * rate limit registers to their initial state.

	 */

	for (i = 0; i < 6; i++)

		REG_WRITE(REG_GLOBAL2, 0x09, 0x9000 | (i << 8));



	/* Initialise cross-chip port VLAN table to reset defaults. */

	REG_WRITE(REG_GLOBAL2, 0x0b, 0x9000);



	/* Clear the priority override table. */

	for (i = 0; i < 16; i++)

		REG_WRITE(REG_GLOBAL2, 0x0f, 0x8000 | (i << 8));



	/* @@@ initialise AVB (22/23) watchdog (27) sdet (29) registers */

	REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL_2, ds->index & 0x1f);



	return 0;

}



static int mv88e6123_61_65_setup_port(struct dsa_switch *ds, int p)

{

	int addr = REG_PORT(p);

	u16 val;



	/* MAC Forcing register: don't force link, speed, duplex

	 * or flow control state to any particular values on physical

	 * ports, but force the CPU port and all DSA ports to 1000 Mb/s

	 * full duplex.

	 */

	if (dsa_is_cpu_port(ds, p) || ds->dsa_port_mask & (1 << p))

		REG_WRITE(addr, 0x01, 0x003e);

	else

		REG_WRITE(addr, 0x01, 0x0003);



	/* Do not limit the period of time that this port can be

	 * paused for by the remote end or the period of time that

	 * this port can pause the remote end.

	 */

	REG_WRITE(addr, 0x02, 0x0000);



	/* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,

	 * disable Header mode, enable IGMP/MLD snooping, disable VLAN

	 * tunneling, determine priority by looking at 802.1p and IP

	 * priority fields (IP prio has precedence), and set STP state

	 * to Forwarding.

	 *

	 * If this is the CPU link, use DSA or EDSA tagging depending

	 * on which tagging mode was configured.

	 *

	 * If this is a link to another switch, use DSA tagging mode.

	 *

	 * If this is the upstream port for this switch, enable

	 * forwarding of unknown unicasts and multicasts.

	 */

	val = 0x0433;

	if (dsa_is_cpu_port(ds, p)) {

		if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)

			val |= 0x3300;

		else

			val |= 0x0100;

	}

	if (ds->dsa_port_mask & (1 << p))

		val |= 0x0100;

	if (p == dsa_upstream_port(ds))

		val |= 0x000c;

	REG_WRITE(addr, 0x04, val);



	/* Port Control 2: don't force a good FCS, set the maximum

	 * frame size to 10240 bytes, don't let the switch add or

	 * strip 802.1q tags, don't discard tagged or untagged frames

	 * on this port, do a destination address lookup on all

	 * received packets as usual, disable ARP mirroring and don't

	 * send a copy of all transmitted/received frames on this port

	 * to the CPU.

	 */

	REG_WRITE(addr, 0x08, 0x2080);



	/* Egress rate control: disable egress rate control. */

	REG_WRITE(addr, 0x09, 0x0001);



	/* Egress rate control 2: disable egress rate control. */

	REG_WRITE(addr, 0x0a, 0x0000);



	/* Port Association Vector: when learning source addresses

	 * of packets, add the address to the address database using

	 * a port bitmap that has only the bit for this port set and

	 * the other bits clear.

	 */

	REG_WRITE(addr, 0x0b, 1 << p);



	/* Port ATU control: disable limiting the number of address

	 * database entries that this port is allowed to use.

	 */

	REG_WRITE(addr, 0x0c, 0x0000);



	/* Priority Override: disable DA, SA and VTU priority override. */

	REG_WRITE(addr, 0x0d, 0x0000);



	/* Port Ethertype: use the Ethertype DSA Ethertype value. */

	REG_WRITE(addr, 0x0f, ETH_P_EDSA);



	/* Tag Remap: use an identity 802.1p prio -> switch prio

	 * mapping.

	 */

	REG_WRITE(addr, 0x18, 0x3210);



	/* Tag Remap 2: use an identity 802.1p prio -> switch prio

	 * mapping.

	 */

	REG_WRITE(addr, 0x19, 0x7654);



	return mv88e6xxx_setup_port_common(ds, p);

}



static int mv88e6123_61_65_setup(struct dsa_switch *ds)

{

	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);

	int i;

	int ret;



	ret = mv88e6xxx_setup_common(ds);
@@ -262,19 +110,11 @@ static int mv88e6123_61_65_setup(struct dsa_switch *ds) 
	if (ret < 0)

		return ret;



	/* @@@ initialise vtu and atu */



	ret = mv88e6123_61_65_setup_global(ds);

	if (ret < 0)

		return ret;



	for (i = 0; i < ps->num_ports; i++) {

		ret = mv88e6123_61_65_setup_port(ds, i);

		if (ret < 0)

			return ret;

	}



	return 0;

	return mv88e6xxx_setup_ports(ds);

}



struct dsa_switch_driver mv88e6123_61_65_switch_driver = {

drivers/net/dsa/mv88e6131.c

+28 −157
Original line number Diff line number Diff line
@@ -37,6 +37,8 @@ static char *mv88e6131_probe(struct device *host_dev, int sw_addr) 
			return "Marvell 88E6131 (B2)";

		if (ret_masked == PORT_SWITCH_ID_6131)

			return "Marvell 88E6131";

		if (ret_masked == PORT_SWITCH_ID_6185)

			return "Marvell 88E6185";

	}



	return NULL;
@@ -44,186 +46,62 @@ static char *mv88e6131_probe(struct device *host_dev, int sw_addr) 


static int mv88e6131_setup_global(struct dsa_switch *ds)

{

	u32 upstream_port = dsa_upstream_port(ds);

	int ret;

	int i;

	u32 reg;



	ret = mv88e6xxx_setup_global(ds);

	if (ret)

		return ret;



	/* Enable the PHY polling unit, don't discard packets with

	 * excessive collisions, use a weighted fair queueing scheme

	 * to arbitrate between packet queues, set the maximum frame

	 * size to 1632, and mask all interrupt sources.

	 */

	REG_WRITE(REG_GLOBAL, 0x04, 0x4400);



	/* Set the default address aging time to 5 minutes, and

	 * enable address learn messages to be sent to all message

	 * ports.

	 */

	REG_WRITE(REG_GLOBAL, 0x0a, 0x0148);



	/* Configure the priority mapping registers. */

	ret = mv88e6xxx_config_prio(ds);

	if (ret < 0)

		return ret;

	REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL,

		  GLOBAL_CONTROL_PPU_ENABLE | GLOBAL_CONTROL_MAX_FRAME_1632);



	/* Set the VLAN ethertype to 0x8100. */

	REG_WRITE(REG_GLOBAL, 0x19, 0x8100);

	REG_WRITE(REG_GLOBAL, GLOBAL_CORE_TAG_TYPE, 0x8100);



	/* Disable ARP mirroring, and configure the upstream port as

	 * the port to which ingress and egress monitor frames are to

	 * be sent.

	 */

	REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1100) | 0x00f0);

	reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |

		upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT |

		GLOBAL_MONITOR_CONTROL_ARP_DISABLED;

	REG_WRITE(REG_GLOBAL, GLOBAL_MONITOR_CONTROL, reg);



	/* Disable cascade port functionality unless this device

	 * is used in a cascade configuration, and set the switch's

	 * DSA device number.

	 */

	if (ds->dst->pd->nr_chips > 1)

		REG_WRITE(REG_GLOBAL, 0x1c, 0xf000 | (ds->index & 0x1f));

		REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL_2,

			  GLOBAL_CONTROL_2_MULTIPLE_CASCADE |

			  (ds->index & 0x1f));

	else

		REG_WRITE(REG_GLOBAL, 0x1c, 0xe000 | (ds->index & 0x1f));



	/* Send all frames with destination addresses matching

	 * 01:80:c2:00:00:0x to the CPU port.

	 */

	REG_WRITE(REG_GLOBAL2, 0x03, 0xffff);



	/* Ignore removed tag data on doubly tagged packets, disable

	 * flow control messages, force flow control priority to the

	 * highest, and send all special multicast frames to the CPU

	 * port at the highest priority.

	 */

	REG_WRITE(REG_GLOBAL2, 0x05, 0x00ff);



	/* Program the DSA routing table. */

	for (i = 0; i < 32; i++) {

		int nexthop;



		nexthop = 0x1f;

		if (ds->pd->rtable &&

		    i != ds->index && i < ds->dst->pd->nr_chips)

			nexthop = ds->pd->rtable[i] & 0x1f;



		REG_WRITE(REG_GLOBAL2, 0x06, 0x8000 | (i << 8) | nexthop);

	}



	/* Clear all trunk masks. */

	for (i = 0; i < 8; i++)

		REG_WRITE(REG_GLOBAL2, 0x07, 0x8000 | (i << 12) | 0x7ff);



	/* Clear all trunk mappings. */

	for (i = 0; i < 16; i++)

		REG_WRITE(REG_GLOBAL2, 0x08, 0x8000 | (i << 11));

		REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL_2,

			  GLOBAL_CONTROL_2_NO_CASCADE |

			  (ds->index & 0x1f));



	/* Force the priority of IGMP/MLD snoop frames and ARP frames

	 * to the highest setting.

	 */

	REG_WRITE(REG_GLOBAL2, 0x0f, 0x00ff);

	REG_WRITE(REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE,

		  GLOBAL2_PRIO_OVERRIDE_FORCE_SNOOP |

		  7 << GLOBAL2_PRIO_OVERRIDE_SNOOP_SHIFT |

		  GLOBAL2_PRIO_OVERRIDE_FORCE_ARP |

		  7 << GLOBAL2_PRIO_OVERRIDE_ARP_SHIFT);



	return 0;

}



static int mv88e6131_setup_port(struct dsa_switch *ds, int p)

{

	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);

	int addr = REG_PORT(p);

	u16 val;



	/* MAC Forcing register: don't force link, speed, duplex

	 * or flow control state to any particular values on physical

	 * ports, but force the CPU port and all DSA ports to 1000 Mb/s

	 * (100 Mb/s on 6085) full duplex.

	 */

	if (dsa_is_cpu_port(ds, p) || ds->dsa_port_mask & (1 << p))

		if (ps->id == PORT_SWITCH_ID_6085)

			REG_WRITE(addr, 0x01, 0x003d); /* 100 Mb/s */

		else

			REG_WRITE(addr, 0x01, 0x003e); /* 1000 Mb/s */

	else

		REG_WRITE(addr, 0x01, 0x0003);



	/* Port Control: disable Core Tag, disable Drop-on-Lock,

	 * transmit frames unmodified, disable Header mode,

	 * enable IGMP/MLD snoop, disable DoubleTag, disable VLAN

	 * tunneling, determine priority by looking at 802.1p and

	 * IP priority fields (IP prio has precedence), and set STP

	 * state to Forwarding.

	 *

	 * If this is the upstream port for this switch, enable

	 * forwarding of unknown unicasts, and enable DSA tagging

	 * mode.

	 *

	 * If this is the link to another switch, use DSA tagging

	 * mode, but do not enable forwarding of unknown unicasts.

	 */

	val = 0x0433;

	if (p == dsa_upstream_port(ds)) {

		val |= 0x0104;

		/* On 6085, unknown multicast forward is controlled

		 * here rather than in Port Control 2 register.

		 */

		if (ps->id == PORT_SWITCH_ID_6085)

			val |= 0x0008;

	}

	if (ds->dsa_port_mask & (1 << p))

		val |= 0x0100;

	REG_WRITE(addr, 0x04, val);



	/* Port Control 2: don't force a good FCS, don't use

	 * VLAN-based, source address-based or destination

	 * address-based priority overrides, don't let the switch

	 * add or strip 802.1q tags, don't discard tagged or

	 * untagged frames on this port, do a destination address

	 * lookup on received packets as usual, don't send a copy

	 * of all transmitted/received frames on this port to the

	 * CPU, and configure the upstream port number.

	 *

	 * If this is the upstream port for this switch, enable

	 * forwarding of unknown multicast addresses.

	 */

	if (ps->id == PORT_SWITCH_ID_6085)

		/* on 6085, bits 3:0 are reserved, bit 6 control ARP

		 * mirroring, and multicast forward is handled in

		 * Port Control register.

		 */

		REG_WRITE(addr, 0x08, 0x0080);

	else {

		val = 0x0080 | dsa_upstream_port(ds);

		if (p == dsa_upstream_port(ds))

			val |= 0x0040;

		REG_WRITE(addr, 0x08, val);

	}



	/* Rate Control: disable ingress rate limiting. */

	REG_WRITE(addr, 0x09, 0x0000);



	/* Rate Control 2: disable egress rate limiting. */

	REG_WRITE(addr, 0x0a, 0x0000);



	/* Port Association Vector: when learning source addresses

	 * of packets, add the address to the address database using

	 * a port bitmap that has only the bit for this port set and

	 * the other bits clear.

	 */

	REG_WRITE(addr, 0x0b, 1 << p);



	/* Tag Remap: use an identity 802.1p prio -> switch prio

	 * mapping.

	 */

	REG_WRITE(addr, 0x18, 0x3210);



	/* Tag Remap 2: use an identity 802.1p prio -> switch prio

	 * mapping.

	 */

	REG_WRITE(addr, 0x19, 0x7654);



	return mv88e6xxx_setup_port_common(ds, p);

}



static int mv88e6131_setup(struct dsa_switch *ds)

{

	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);

	int i;

	int ret;



	ret = mv88e6xxx_setup_common(ds);
@@ -234,6 +112,7 @@ static int mv88e6131_setup(struct dsa_switch *ds) 


	switch (ps->id) {

	case PORT_SWITCH_ID_6085:

	case PORT_SWITCH_ID_6185:

		ps->num_ports = 10;

		break;

	case PORT_SWITCH_ID_6095:
@@ -251,19 +130,11 @@ static int mv88e6131_setup(struct dsa_switch *ds) 
	if (ret < 0)

		return ret;



	/* @@@ initialise vtu and atu */



	ret = mv88e6131_setup_global(ds);

	if (ret < 0)

		return ret;



	for (i = 0; i < ps->num_ports; i++) {

		ret = mv88e6131_setup_port(ds, i);

		if (ret < 0)

			return ret;

	}



	return 0;

	return mv88e6xxx_setup_ports(ds);

}



static int mv88e6131_port_to_phy_addr(struct dsa_switch *ds, int port)

drivers/net/dsa/mv88e6171.c

+25 −209
Original line number Diff line number Diff line 
/* net/dsa/mv88e6171.c - Marvell 88e6171/8826172 switch chip support

/* net/dsa/mv88e6171.c - Marvell 88e6171 switch chip support

 * Copyright (c) 2008-2009 Marvell Semiconductor

 * Copyright (c) 2014 Claudio Leite <leitec@staticky.com>

 *
@@ -29,8 +29,12 @@ static char *mv88e6171_probe(struct device *host_dev, int sw_addr) 
	if (ret >= 0) {

		if ((ret & 0xfff0) == PORT_SWITCH_ID_6171)

			return "Marvell 88E6171";

		if ((ret & 0xfff0) == PORT_SWITCH_ID_6172)

			return "Marvell 88E6172";

		if ((ret & 0xfff0) == PORT_SWITCH_ID_6175)

			return "Marvell 88E6175";

		if ((ret & 0xfff0) == PORT_SWITCH_ID_6350)

			return "Marvell 88E6350";

		if ((ret & 0xfff0) == PORT_SWITCH_ID_6351)

			return "Marvell 88E6351";

	}



	return NULL;
@@ -38,196 +42,41 @@ static char *mv88e6171_probe(struct device *host_dev, int sw_addr) 


static int mv88e6171_setup_global(struct dsa_switch *ds)

{

	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);

	u32 upstream_port = dsa_upstream_port(ds);

	int ret;

	int i;

	u32 reg;



	ret = mv88e6xxx_setup_global(ds);

	if (ret)

		return ret;



	/* Discard packets with excessive collisions, mask all

	 * interrupt sources, enable PPU.

	 */

	REG_WRITE(REG_GLOBAL, 0x04, 0x6000);



	/* Set the default address aging time to 5 minutes, and

	 * enable address learn messages to be sent to all message

	 * ports.

	 */

	REG_WRITE(REG_GLOBAL, 0x0a, 0x0148);



	/* Configure the priority mapping registers. */

	ret = mv88e6xxx_config_prio(ds);

	if (ret < 0)

		return ret;

	REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL,

		  GLOBAL_CONTROL_PPU_ENABLE | GLOBAL_CONTROL_DISCARD_EXCESS);



	/* Configure the upstream port, and configure the upstream

	 * port as the port to which ingress and egress monitor frames

	 * are to be sent.

	 */

	if (REG_READ(REG_PORT(0), 0x03) == 0x1710)

		REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1111));

	else

		REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1110));

	reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |

		upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT |

		upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT |

		upstream_port << GLOBAL_MONITOR_CONTROL_MIRROR_SHIFT;

	REG_WRITE(REG_GLOBAL, GLOBAL_MONITOR_CONTROL, reg);



	/* Disable remote management for now, and set the switch's

	 * DSA device number.

	 */

	REG_WRITE(REG_GLOBAL, 0x1c, ds->index & 0x1f);



	/* Send all frames with destination addresses matching

	 * 01:80:c2:00:00:2x to the CPU port.

	 */

	REG_WRITE(REG_GLOBAL2, 0x02, 0xffff);



	/* Send all frames with destination addresses matching

	 * 01:80:c2:00:00:0x to the CPU port.

	 */

	REG_WRITE(REG_GLOBAL2, 0x03, 0xffff);



	/* Disable the loopback filter, disable flow control

	 * messages, disable flood broadcast override, disable

	 * removing of provider tags, disable ATU age violation

	 * interrupts, disable tag flow control, force flow

	 * control priority to the highest, and send all special

	 * multicast frames to the CPU at the highest priority.

	 */

	REG_WRITE(REG_GLOBAL2, 0x05, 0x00ff);



	/* Program the DSA routing table. */

	for (i = 0; i < 32; i++) {

		int nexthop;



		nexthop = 0x1f;

		if (i != ds->index && i < ds->dst->pd->nr_chips)

			nexthop = ds->pd->rtable[i] & 0x1f;



		REG_WRITE(REG_GLOBAL2, 0x06, 0x8000 | (i << 8) | nexthop);

	}



	/* Clear all trunk masks. */

	for (i = 0; i < ps->num_ports; i++)

		REG_WRITE(REG_GLOBAL2, 0x07, 0x8000 | (i << 12) | 0xff);



	/* Clear all trunk mappings. */

	for (i = 0; i < 16; i++)

		REG_WRITE(REG_GLOBAL2, 0x08, 0x8000 | (i << 11));



	/* Disable ingress rate limiting by resetting all ingress

	 * rate limit registers to their initial state.

	 */

	for (i = 0; i < 6; i++)

		REG_WRITE(REG_GLOBAL2, 0x09, 0x9000 | (i << 8));



	/* Initialise cross-chip port VLAN table to reset defaults. */

	REG_WRITE(REG_GLOBAL2, 0x0b, 0x9000);



	/* Clear the priority override table. */

	for (i = 0; i < 16; i++)

		REG_WRITE(REG_GLOBAL2, 0x0f, 0x8000 | (i << 8));



	/* @@@ initialise AVB (22/23) watchdog (27) sdet (29) registers */

	REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL_2, ds->index & 0x1f);



	return 0;

}



static int mv88e6171_setup_port(struct dsa_switch *ds, int p)

{

	int addr = REG_PORT(p);

	u16 val;



	/* MAC Forcing register: don't force link, speed, duplex

	 * or flow control state to any particular values on physical

	 * ports, but force the CPU port and all DSA ports to 1000 Mb/s

	 * full duplex.

	 */

	val = REG_READ(addr, 0x01);

	if (dsa_is_cpu_port(ds, p) || ds->dsa_port_mask & (1 << p))

		REG_WRITE(addr, 0x01, val | 0x003e);

	else

		REG_WRITE(addr, 0x01, val | 0x0003);



	/* Do not limit the period of time that this port can be

	 * paused for by the remote end or the period of time that

	 * this port can pause the remote end.

	 */

	REG_WRITE(addr, 0x02, 0x0000);



	/* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,

	 * disable Header mode, enable IGMP/MLD snooping, disable VLAN

	 * tunneling, determine priority by looking at 802.1p and IP

	 * priority fields (IP prio has precedence), and set STP state

	 * to Forwarding.

	 *

	 * If this is the CPU link, use DSA or EDSA tagging depending

	 * on which tagging mode was configured.

	 *

	 * If this is a link to another switch, use DSA tagging mode.

	 *

	 * If this is the upstream port for this switch, enable

	 * forwarding of unknown unicasts and multicasts.

	 */

	val = 0x0433;

	if (dsa_is_cpu_port(ds, p)) {

		if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)

			val |= 0x3300;

		else

			val |= 0x0100;

	}

	if (ds->dsa_port_mask & (1 << p))

		val |= 0x0100;

	if (p == dsa_upstream_port(ds))

		val |= 0x000c;

	REG_WRITE(addr, 0x04, val);



	/* Port Control 2: don't force a good FCS, set the maximum

	 * frame size to 10240 bytes, don't let the switch add or

	 * strip 802.1q tags, don't discard tagged or untagged frames

	 * on this port, do a destination address lookup on all

	 * received packets as usual, disable ARP mirroring and don't

	 * send a copy of all transmitted/received frames on this port

	 * to the CPU.

	 */

	REG_WRITE(addr, 0x08, 0x2080);



	/* Egress rate control: disable egress rate control. */

	REG_WRITE(addr, 0x09, 0x0001);



	/* Egress rate control 2: disable egress rate control. */

	REG_WRITE(addr, 0x0a, 0x0000);



	/* Port Association Vector: when learning source addresses

	 * of packets, add the address to the address database using

	 * a port bitmap that has only the bit for this port set and

	 * the other bits clear.

	 */

	REG_WRITE(addr, 0x0b, 1 << p);



	/* Port ATU control: disable limiting the number of address

	 * database entries that this port is allowed to use.

	 */

	REG_WRITE(addr, 0x0c, 0x0000);



	/* Priority Override: disable DA, SA and VTU priority override. */

	REG_WRITE(addr, 0x0d, 0x0000);



	/* Port Ethertype: use the Ethertype DSA Ethertype value. */

	REG_WRITE(addr, 0x0f, ETH_P_EDSA);



	/* Tag Remap: use an identity 802.1p prio -> switch prio

	 * mapping.

	 */

	REG_WRITE(addr, 0x18, 0x3210);



	/* Tag Remap 2: use an identity 802.1p prio -> switch prio

	 * mapping.

	 */

	REG_WRITE(addr, 0x19, 0x7654);



	return mv88e6xxx_setup_port_common(ds, p);

}



static int mv88e6171_setup(struct dsa_switch *ds)

{

	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);

	int i;

	int ret;



	ret = mv88e6xxx_setup_common(ds);
@@ -240,44 +89,11 @@ static int mv88e6171_setup(struct dsa_switch *ds) 
	if (ret < 0)

		return ret;



	/* @@@ initialise vtu and atu */



	ret = mv88e6171_setup_global(ds);

	if (ret < 0)

		return ret;



	for (i = 0; i < ps->num_ports; i++) {

		if (!(dsa_is_cpu_port(ds, i) || ds->phys_port_mask & (1 << i)))

			continue;



		ret = mv88e6171_setup_port(ds, i);

		if (ret < 0)

			return ret;

	}



	return 0;

}



static int mv88e6171_get_eee(struct dsa_switch *ds, int port,

			     struct ethtool_eee *e)

{

	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);



	if (ps->id == PORT_SWITCH_ID_6172)

		return mv88e6xxx_get_eee(ds, port, e);



	return -EOPNOTSUPP;

}



static int mv88e6171_set_eee(struct dsa_switch *ds, int port,

			     struct phy_device *phydev, struct ethtool_eee *e)

{

	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);



	if (ps->id == PORT_SWITCH_ID_6172)

		return mv88e6xxx_set_eee(ds, port, phydev, e);



	return -EOPNOTSUPP;

	return mv88e6xxx_setup_ports(ds);

}



struct dsa_switch_driver mv88e6171_switch_driver = {
@@ -292,8 +108,6 @@ struct dsa_switch_driver mv88e6171_switch_driver = { 
	.get_strings		= mv88e6xxx_get_strings,

	.get_ethtool_stats	= mv88e6xxx_get_ethtool_stats,

	.get_sset_count		= mv88e6xxx_get_sset_count,

	.set_eee		= mv88e6171_set_eee,

	.get_eee		= mv88e6171_get_eee,

#ifdef CONFIG_NET_DSA_HWMON

	.get_temp               = mv88e6xxx_get_temp,

#endif
@@ -308,4 +122,6 @@ struct dsa_switch_driver mv88e6171_switch_driver = { 
};



MODULE_ALIAS("platform:mv88e6171");

MODULE_ALIAS("platform:mv88e6172");
 
MODULE_ALIAS("platform:mv88e6175");

MODULE_ALIAS("platform:mv88e6350");

MODULE_ALIAS("platform:mv88e6351");

drivers/net/dsa/mv88e6352.c

+16 −172

File changed.

Preview size limit exceeded, changes collapsed.