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Commit f795f9a6 authored by Venkat Gopalakrishnan's avatar Venkat Gopalakrishnan
Browse files

ARM: dts: msm: enable aggre1 ufs hw ctl clock for msmcobalt 



QCOM UFS host controller v3.0.0 supports hw gating of clocks,
enable the use of hw ctl clock variant of aggre1 ufs clock.

Change-Id: I3f0e718362a73c2c440fa2b0aea816fa058fdaa3
Signed-off-by: default avatarVenkat Gopalakrishnan <venkatg@codeaurora.org>
parent 7c179541

arch/arm/boot/dts/qcom/msmcobalt.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -1697,7 +1697,7 @@ 
			"rx_lane0_sync_clk";

		clocks =

			<&clock_gcc clk_gcc_ufs_axi_hw_ctl_clk>,

			<&clock_gcc clk_gcc_aggre1_ufs_axi_clk>,

			<&clock_gcc clk_gcc_aggre1_ufs_axi_hw_ctl_clk>,

			<&clock_gcc clk_gcc_ufs_ahb_clk>,

			<&clock_gcc clk_gcc_ufs_unipro_core_hw_ctl_clk>,

			<&clock_gcc clk_gcc_ufs_ice_core_hw_ctl_clk>,