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Commit f556cace authored by Amit Nischal's avatar Amit Nischal Committed by Venkat Gopalakrishnan
Browse files

scsi: ufs: Add support for reset controller framework 



The current api which performs the clock reset is moved to use the reset
framework, so support the changes in ufs driver for the same. The reset
framework requires to get reset handle and perform assert/deassert of the
resets.

Change-Id: I78d833639772cf541e563cbf9fae1aa75ec6a7da
Signed-off-by: default avatarAmit Nischal <anischal@codeaurora.org>
parent 9b82a4c5

Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt

+5 −0
Original line number Diff line number Diff line
@@ -13,6 +13,9 @@ Required properties: 
- reg               : <registers mapping>

		      first entry should contain UFS host controller register address space (mandatory),

                      second entry is the device ref. clock control register map (optional).

- reset             : reset specifier pair consists of phandle for the reset provider

                      and reset lines used by this controller.

- reset-names       : reset signal name strings sorted in the same order as the resets property.



Optional properties:

- phys                  : phandle to UFS PHY node
@@ -76,6 +79,8 @@ Example: 
		clocks = <&core 0>, <&ref 0>, <&iface 0>;

		clock-names = "core_clk", "ref_clk", "iface_clk";

		freq-table-hz = <100000000 200000000>, <0 0>, <0 0>;

		resets = <clock_gcc GCC_UFS_BCR>;

		reset-names = "core_reset";

		phys = <&ufsphy1>;

		phy-names = "ufsphy";

		rpm-level = <3>;

arch/arm/boot/dts/qcom/msm8996.dtsi

+3 −0
Original line number Diff line number Diff line
@@ -1246,6 +1246,9 @@ 
		"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1",

		"MAX";



		resets = <&clock_gcc UFS_BCR>;

		reset-names = "core_reset";



		/* PM QoS */

		qcom,pm-qos-cpu-groups = <0x03 0x0C>;

		qcom,pm-qos-cpu-group-latency-us = <70 70>;

arch/arm/boot/dts/qcom/msmcobalt.dtsi

+3 −0
Original line number Diff line number Diff line
@@ -1791,6 +1791,9 @@ 
		qcom,pm-qos-cpu-group-latency-us = <70 70>;

		qcom,pm-qos-default-cpu = <0>;



		resets = <&clock_gcc UFS_BCR>;

		reset-names = "core_reset";



		status = "disabled";

	};

drivers/scsi/ufs/ufs-qcom.c

+20 −12
Original line number Diff line number Diff line
@@ -764,21 +764,29 @@ out: 


static int ufs_qcom_full_reset(struct ufs_hba *hba)

{

	struct ufs_clk_info *clki;

	int ret = -ENOTSUPP;



	list_for_each_entry(clki, &hba->clk_list_head, list) {

		if (!strcmp(clki->name, "core_clk")) {

			ret = clk_reset(clki->clk, CLK_RESET_ASSERT);

			if (ret)

	if (!hba->core_reset) {

		dev_err(hba->dev, "%s: failed, err = %d\n", __func__,

				ret);

		goto out;

	}



	ret = reset_control_assert(hba->core_reset);

	if (ret) {

		dev_err(hba->dev, "%s: core_reset assert failed, err = %d\n",

				__func__, ret);

		goto out;

	}



	/* Very small delay, per the documented requirement */

	usleep_range(1, 2);



			ret = clk_reset(clki->clk, CLK_RESET_DEASSERT);

			break;

		}

	}

	ret = reset_control_deassert(hba->core_reset);

	if (ret)

		dev_err(hba->dev, "%s: core_reset deassert failed, err = %d\n",

				__func__, ret);



out:

	return ret;

}

drivers/scsi/ufs/ufshcd-pltfrm.c

+23 −0
Original line number Diff line number Diff line
@@ -40,6 +40,22 @@ 
#include "ufshcd.h"

#include "ufshcd-pltfrm.h"



static int ufshcd_parse_reset_info(struct ufs_hba *hba)

{

	int ret = 0;



	hba->core_reset = devm_reset_control_get(hba->dev,

				"core_reset");

	if (IS_ERR(hba->core_reset)) {

		ret = PTR_ERR(hba->core_reset);

		dev_err(hba->dev, "core_reset unavailable,err = %d\n",

				ret);

		hba->core_reset = NULL;

	}



	return ret;

}



static int ufshcd_parse_clock_info(struct ufs_hba *hba)

{

	int ret = 0;
@@ -338,6 +354,13 @@ int ufshcd_pltfrm_init(struct platform_device *pdev, 
		goto dealloc_host;

	}



	err = ufshcd_parse_reset_info(hba);

	if (err) {

		dev_err(&pdev->dev, "%s: reset parse failed %d\n",

				__func__, err);

		goto dealloc_host;

	}



	ufshcd_parse_pm_levels(hba);



	if (!dev->dma_mask)