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Commit f44d9e36 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: update CPU efficiency values for sdm660"

parents 2081c638 4e258da2

arch/arm/boot/dts/qcom/sdm660.dtsi

+4 −4
Original line number Diff line number Diff line
@@ -152,7 +152,7 @@ 
			qcom,limits-info = <&mitigation_profile1>;

			qcom,lmh-dcvs = <&lmh_dcvs1>;

			qcom,ea = <&ea4>;

			efficiency = <1536>;

			efficiency = <1638>;

			next-level-cache = <&L2_1>;

			L2_1: l2-cache {

				compatible = "arm,arch-cache";
@@ -179,7 +179,7 @@ 
			qcom,limits-info = <&mitigation_profile2>;

			qcom,lmh-dcvs = <&lmh_dcvs1>;

			qcom,ea = <&ea5>;

			efficiency = <1536>;

			efficiency = <1638>;

			next-level-cache = <&L2_1>;

			L1_I_101: l1-icache {

				compatible = "arm,arch-cache";
@@ -202,7 +202,7 @@ 
			qcom,limits-info = <&mitigation_profile3>;

			qcom,lmh-dcvs = <&lmh_dcvs1>;

			qcom,ea = <&ea6>;

			efficiency = <1536>;

			efficiency = <1638>;

			next-level-cache = <&L2_1>;

			L1_I_102: l1-icache {

				compatible = "arm,arch-cache";
@@ -225,7 +225,7 @@ 
			qcom,limits-info = <&mitigation_profile4>;

			qcom,lmh-dcvs = <&lmh_dcvs1>;

			qcom,ea = <&ea7>;

			efficiency = <1536>;

			efficiency = <1638>;

			next-level-cache = <&L2_1>;

			L1_I_103: l1-icache {

				compatible = "arm,arch-cache";