Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit f31f2d55 authored by Paulo Zanoni's avatar Paulo Zanoni Committed by Daniel Vetter
Browse files

drm/i915: extract FDI mPHY functions from lpt_init_pch_refclk 



Because lpt_init_pch_refclk implements the "Sequence to enable
CLKOUT_DP for FDI usage and configure PCH FDI I/O", which is very
similar to "Sequence to enable CLKOUT_DP" and "Sequence to enable
CLKOUT_DP without spread". With the extracted functions we can more
easily implement the two missing sequences.

v2: Rebase (WaMPhyProgramming:hsw comment).

Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: default avatarBen Widawsky <ben@bwidawsk.net>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 0ff066a9

drivers/gpu/drm/i915/intel_display.c

+45 −34
Original line number Diff line number Diff line
@@ -5167,41 +5167,9 @@ static void ironlake_init_pch_refclk(struct drm_device *dev) 
	BUG_ON(val != final);

}



/*

 * Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O.

 * WaMPhyProgramming:hsw

 */

static void lpt_init_pch_refclk(struct drm_device *dev)

static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct drm_mode_config *mode_config = &dev->mode_config;

	struct intel_encoder *encoder;

	bool has_vga = false;

	u32 tmp;



	list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {

		switch (encoder->type) {

		case INTEL_OUTPUT_ANALOG:

			has_vga = true;

			break;

		}

	}



	if (!has_vga)

		return;



	mutex_lock(&dev_priv->dpio_lock);



	tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);

	tmp &= ~SBI_SSCCTL_DISABLE;

	tmp |= SBI_SSCCTL_PATHALT;

	intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);



	udelay(24);



	tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);

	tmp &= ~SBI_SSCCTL_PATHALT;

	intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);

	uint32_t tmp;



	tmp = I915_READ(SOUTH_CHICKEN2);

	tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
@@ -5218,6 +5186,12 @@ static void lpt_init_pch_refclk(struct drm_device *dev) 
	if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &

				FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))

		DRM_ERROR("FDI mPHY reset de-assert timeout\n");

}



/* WaMPhyProgramming:hsw */

static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)

{

	uint32_t tmp;



	tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);

	tmp &= ~(0xFF << 24);
@@ -5287,6 +5261,43 @@ static void lpt_init_pch_refclk(struct drm_device *dev) 
	tmp &= ~(0xF << 28);

	tmp |= (4 << 28);

	intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);

}



/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */

static void lpt_init_pch_refclk(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct drm_mode_config *mode_config = &dev->mode_config;

	struct intel_encoder *encoder;

	bool has_vga = false;

	u32 tmp;



	list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {

		switch (encoder->type) {

		case INTEL_OUTPUT_ANALOG:

			has_vga = true;

			break;

		}

	}



	if (!has_vga)

		return;



	mutex_lock(&dev_priv->dpio_lock);



	tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);

	tmp &= ~SBI_SSCCTL_DISABLE;

	tmp |= SBI_SSCCTL_PATHALT;

	intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);



	udelay(24);



	tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);

	tmp &= ~SBI_SSCCTL_PATHALT;

	intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);



	lpt_reset_fdi_mphy(dev_priv);

	lpt_program_fdi_mphy(dev_priv);



	/* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */

	tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);