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Commit f1d29a3f authored by Ben Hutchings's avatar Ben Hutchings Committed by David S. Miller
Browse files

mlx4_en: Remove remnants of LRO support



Commit fa37a958 ('mlx4_en: Moving to
work with GRO') left behind the Kconfig depends/select, some dead
code and comments referring to LRO.

Signed-off-by: default avatarBen Hutchings <bhutchings@solarflare.com>
Acked-by: default avatarAmir Vadai <amirv@mellanox.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 01f1c6b9
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+1 −2
Original line number Diff line number Diff line
@@ -4,9 +4,8 @@

config MLX4_EN
	tristate "Mellanox Technologies 10Gbit Ethernet support"
	depends on PCI && INET
	depends on PCI
	select MLX4_CORE
	select INET_LRO
	---help---
	  This driver supports Mellanox Technologies ConnectX Ethernet
	  devices.
+3 −6
Original line number Diff line number Diff line
@@ -630,7 +630,7 @@ int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int bud
			if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) &&
			    (cqe->checksum == cpu_to_be16(0xffff))) {
				ring->csum_ok++;
				/* This packet is eligible for LRO if it is:
				/* This packet is eligible for GRO if it is:
				 * - DIX Ethernet (type interpretation)
				 * - TCP/IP (v4)
				 * - without IP options
@@ -667,7 +667,7 @@ int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int bud
					goto next;
				}

				/* LRO not possible, complete processing here */
				/* GRO not possible, complete processing here */
				ip_summed = CHECKSUM_UNNECESSARY;
			} else {
				ip_summed = CHECKSUM_NONE;
@@ -710,12 +710,9 @@ next:
		++cq->mcq.cons_index;
		index = (cq->mcq.cons_index) & ring->size_mask;
		cqe = &cq->buf[index];
		if (++polled == budget) {
			/* We are here because we reached the NAPI budget -
			 * flush only pending LRO sessions */
		if (++polled == budget)
			goto out;
	}
	}

out:
	AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled);
+0 −17
Original line number Diff line number Diff line
@@ -95,8 +95,6 @@
#define MLX4_EN_ALLOC_SIZE	PAGE_ALIGN(16384)
#define MLX4_EN_ALLOC_ORDER	get_order(MLX4_EN_ALLOC_SIZE)

#define MLX4_EN_MAX_LRO_DESCRIPTORS	32

/* Receive fragment sizes; we use at most 4 fragments (for 9600 byte MTU
 * and 4K allocations) */
enum {
@@ -290,21 +288,6 @@ struct mlx4_en_rx_ring {
	unsigned long csum_none;
};


static inline int mlx4_en_can_lro(__be16 status)
{
	return (status & cpu_to_be16(MLX4_CQE_STATUS_IPV4	|
				     MLX4_CQE_STATUS_IPV4F	|
				     MLX4_CQE_STATUS_IPV6	|
				     MLX4_CQE_STATUS_IPV4OPT	|
				     MLX4_CQE_STATUS_TCP	|
				     MLX4_CQE_STATUS_UDP	|
				     MLX4_CQE_STATUS_IPOK)) ==
		cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
			    MLX4_CQE_STATUS_IPOK |
			    MLX4_CQE_STATUS_TCP);
}

struct mlx4_en_cq {
	struct mlx4_cq          mcq;
	struct mlx4_hwq_resources wqres;