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Commit f1b714bb authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/net-next 



Jeff Kirsher says:

====================
Intel Wired LAN Driver Updates 2014-07-25

This series contains updates to e1000e, ixgbe and ixgbevf.

Mark provides all the changes for ixgbe and ixgbevf.  Converts some udelay()
calls to the preferred usleep_range().  Fixes a spurious release of the
semaphore in several functions when there was a failure to acquire the
semaphore in the first place.  Fixes a X540 semaphore error where an
incorrect check was treating success as failure and vice-versa.  Fixed
ixgbe_write_mbx() error when it was being called and there was no
mbx->ops.write method defined, so no error code was returned.  The
corresponding read function would explicitly return an error in such a
case as do other functions.  Cleans up unused (dead) code by removing it.
Finally make return values more direct, eliminating some gotos and
otherwise unneeded conditionals, which allows the removal of some local
variables.

David provides all the changes for e1000e.  Fix CRC errors with jumbo
traffic for 82579, i217 and i218 client parts to increase the gap
between the read and write pointers in the transmit FIFO.  Added code
to check and respond to previously ignored return values from NVM
access functions.  Added support for EEE in Sx states and fixed EEE in
S5 with runtime PM enabled.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 6ceed786 2a7e19af

drivers/net/ethernet/intel/e1000e/defines.h

+1 −0
Original line number Diff line number Diff line
@@ -342,6 +342,7 @@ 
#define E1000_TIPG_IPGR2_SHIFT  20



#define MAX_JUMBO_FRAME_SIZE    0x3F00

#define E1000_TX_PTR_GAP		0x1F



/* Extended Configuration Control and Size */

#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP      0x00000020

drivers/net/ethernet/intel/e1000e/ich8lan.c

+17 −3
Original line number Diff line number Diff line
@@ -2444,7 +2444,7 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) 
			return ret_val;

		e1e_rphy(hw, PHY_REG(776, 20), &data);

		data &= ~(0x3FF << 2);

		data |= (0x1A << 2);

		data |= (E1000_TX_PTR_GAP << 2);

		ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);

		if (ret_val)

			return ret_val;
@@ -4605,14 +4605,23 @@ void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw) 


			/* Disable LPLU if both link partners support 100BaseT

			 * EEE and 100Full is advertised on both ends of the

			 * link.

			 * link, and enable Auto Enable LPI since there will

			 * be no driver to enable LPI while in Sx.

			 */

			if ((eee_advert & I82579_EEE_100_SUPPORTED) &&

			    (dev_spec->eee_lp_ability &

			     I82579_EEE_100_SUPPORTED) &&

			    (hw->phy.autoneg_advertised & ADVERTISE_100_FULL))

			    (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {

				phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |

					      E1000_PHY_CTRL_NOND0A_LPLU);



				/* Set Auto Enable LPI after link up */

				e1e_rphy_locked(hw,

						I217_LPI_GPIO_CTRL, &phy_reg);

				phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;

				e1e_wphy_locked(hw,

						I217_LPI_GPIO_CTRL, phy_reg);

			}

		}



		/* For i217 Intel Rapid Start Technology support,
@@ -4709,6 +4718,11 @@ void e1000_resume_workarounds_pchlan(struct e1000_hw *hw) 
			return;

		}



		/* Clear Auto Enable LPI after link up */

		e1e_rphy_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);

		phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;

		e1e_wphy_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);



		if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {

			/* Restore clear on SMB if no manageability engine

			 * is present

drivers/net/ethernet/intel/e1000e/ich8lan.h

+4 −0
Original line number Diff line number Diff line
@@ -217,6 +217,10 @@ 
#define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK	0x3F00

#define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT	8



/* Low Power Idle GPIO Control */

#define I217_LPI_GPIO_CTRL			PHY_REG(772, 18)

#define I217_LPI_GPIO_CTRL_AUTO_EN_LPI		0x0800



/* PHY Low Power Idle Control */

#define I82579_LPI_CTRL				PHY_REG(772, 20)

#define I82579_LPI_CTRL_100_ENABLE		0x2000

drivers/net/ethernet/intel/e1000e/manage.c

+4 −1
Original line number Diff line number Diff line
@@ -327,9 +327,12 @@ bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw) 
	} else if ((hw->mac.type == e1000_82574) ||

		   (hw->mac.type == e1000_82583)) {

		u16 data;

		s32 ret_val;



		factps = er32(FACTPS);

		e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);

		ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);

		if (ret_val)

			return false;



		if (!(factps & E1000_FACTPS_MNGCG) &&

		    ((data & E1000_NVM_INIT_CTRL2_MNGM) ==

drivers/net/ethernet/intel/e1000e/netdev.c

+48 −7
Original line number Diff line number Diff line
@@ -6033,6 +6033,28 @@ release: 
	return retval;

}



static void e1000e_flush_lpic(struct pci_dev *pdev)

{

	struct net_device *netdev = pci_get_drvdata(pdev);

	struct e1000_adapter *adapter = netdev_priv(netdev);

	struct e1000_hw *hw = &adapter->hw;

	u32 ret_val;



	pm_runtime_get_sync(netdev->dev.parent);



	ret_val = hw->phy.ops.acquire(hw);

	if (ret_val)

		goto fl_out;



	pr_info("EEE TX LPI TIMER: %08X\n",

		er32(LPIC) >> E1000_LPIC_LPIET_SHIFT);



	hw->phy.ops.release(hw);



fl_out:

	pm_runtime_put_sync(netdev->dev.parent);

}



static int e1000e_pm_freeze(struct device *dev)

{

	struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));
@@ -6333,6 +6355,8 @@ static int e1000e_pm_suspend(struct device *dev) 
{

	struct pci_dev *pdev = to_pci_dev(dev);



	e1000e_flush_lpic(pdev);



	e1000e_pm_freeze(dev);



	return __e1000_shutdown(pdev, false);
@@ -6357,9 +6381,14 @@ static int e1000e_pm_runtime_idle(struct device *dev) 
	struct pci_dev *pdev = to_pci_dev(dev);

	struct net_device *netdev = pci_get_drvdata(pdev);

	struct e1000_adapter *adapter = netdev_priv(netdev);

	u16 eee_lp;



	if (!e1000e_has_link(adapter))

	eee_lp = adapter->hw.dev_spec.ich8lan.eee_lp_ability;



	if (!e1000e_has_link(adapter)) {

		adapter->hw.dev_spec.ich8lan.eee_lp_ability = eee_lp;

		pm_schedule_suspend(dev, 5 * MSEC_PER_SEC);

	}



	return -EBUSY;

}
@@ -6411,6 +6440,8 @@ static int e1000e_pm_runtime_suspend(struct device *dev) 


static void e1000_shutdown(struct pci_dev *pdev)

{

	e1000e_flush_lpic(pdev);



	e1000e_pm_freeze(&pdev->dev);



	__e1000_shutdown(pdev, false);
@@ -6708,6 +6739,7 @@ static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 
	int bars, i, err, pci_using_dac;

	u16 eeprom_data = 0;

	u16 eeprom_apme_mask = E1000_EEPROM_APME;

	s32 rval = 0;



	if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S)

		aspm_disable_flag = PCIE_LINK_STATE_L0S;
@@ -6940,15 +6972,19 @@ static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 
	} else if (adapter->flags & FLAG_APME_IN_CTRL3) {

		if (adapter->flags & FLAG_APME_CHECK_PORT_B &&

		    (adapter->hw.bus.func == 1))

			e1000_read_nvm(&adapter->hw, NVM_INIT_CONTROL3_PORT_B,

			rval = e1000_read_nvm(&adapter->hw,

					      NVM_INIT_CONTROL3_PORT_B,

					      1, &eeprom_data);

		else

			e1000_read_nvm(&adapter->hw, NVM_INIT_CONTROL3_PORT_A,

			rval = e1000_read_nvm(&adapter->hw,

					      NVM_INIT_CONTROL3_PORT_A,

					      1, &eeprom_data);

	}



	/* fetch WoL from EEPROM */

	if (eeprom_data & eeprom_apme_mask)

	if (rval)

		e_dbg("NVM read error getting WoL initial values: %d\n", rval);

	else if (eeprom_data & eeprom_apme_mask)

		adapter->eeprom_wol |= E1000_WUFC_MAG;



	/* now that we have the eeprom settings, apply the special cases
@@ -6967,7 +7003,12 @@ static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 
		device_wakeup_enable(&pdev->dev);



	/* save off EEPROM version number */

	e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers);

	rval = e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers);



	if (rval) {

		e_dbg("NVM read error getting EEPROM version: %d\n", rval);

		adapter->eeprom_vers = 0;

	}



	/* reset the hardware with the new settings */

	e1000e_reset(adapter);