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Commit f120e77b authored by Aravind Venkateswaran's avatar Aravind Venkateswaran Committed by Gerrit - the friendly Code Review server
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msm: mdss: dp: restrict list of supported modes based on link parameters 



DP sink specifies the maximum per-lane link rate and the maximum lane
count that it supports as part of its capabilities. This would limit
the maximum data transfer rate that can be supported on the link. Use
this information to filter the list of EDID modes to include only the
ones that can be supported with the maximum possible link rate.

CRs-Fixed: 2018514
Change-Id: I4bc3a339935a49081bd45cb778737116d99ee7c2
Signed-off-by: default avatarAravind Venkateswaran <aravindh@codeaurora.org>
parent 6f55033e

drivers/video/fbdev/msm/mdss_dp.c

+22 −0
Original line number Diff line number Diff line
@@ -1290,6 +1290,23 @@ exit: 
	return ret;

}



static u32 mdss_dp_calc_max_pclk_rate(struct mdss_dp_drv_pdata *dp)

{

	u32 bpp = mdss_dp_get_bpp(dp);

	u32 max_link_rate_khz = dp->dpcd.max_link_rate *

		(DP_LINK_RATE_MULTIPLIER / 100);

	u32 max_data_rate_khz = dp->dpcd.max_lane_count *

				max_link_rate_khz * 8 / 10;

	u32 max_pclk_rate_khz = max_data_rate_khz / bpp;



	pr_debug("bpp=%d, max_lane_cnt=%d, max_link_rate=%dKHz\n", bpp,

		dp->dpcd.max_lane_count, max_link_rate_khz);

	pr_debug("max_data_rate=%dKHz, max_pclk_rate=%dKHz\n",

		max_data_rate_khz, max_pclk_rate_khz);



	return max_pclk_rate_khz;

}



static void mdss_dp_set_clock_rate(struct mdss_dp_drv_pdata *dp,

		char *name, u32 rate)

{
@@ -1981,6 +1998,7 @@ end: 
static int mdss_dp_process_hpd_high(struct mdss_dp_drv_pdata *dp)

{

	int ret;

	u32 max_pclk_khz;



	if (dp->sink_info_read)

		return 0;
@@ -1998,6 +2016,10 @@ static int mdss_dp_process_hpd_high(struct mdss_dp_drv_pdata *dp) 
		goto notify;

	}



	max_pclk_khz = mdss_dp_calc_max_pclk_rate(dp);

	hdmi_edid_set_max_pclk_rate(dp->panel_data.panel_info.edid_data,

		min(dp->max_pclk_khz, max_pclk_khz));



	ret = hdmi_edid_parser(dp->panel_data.panel_info.edid_data);

	if (ret) {

		pr_err("edid parse failed, setting default resolution\n");

drivers/video/fbdev/msm/mdss_hdmi_edid.c

+7 −0
Original line number Diff line number Diff line
@@ -2620,6 +2620,13 @@ void hdmi_edid_config_override(void *input, bool enable, 
	}

}



void hdmi_edid_set_max_pclk_rate(void *input, u32 max_pclk_khz)

{

	struct hdmi_edid_ctrl *edid_ctrl = (struct hdmi_edid_ctrl *)input;



	edid_ctrl->init_data.max_pclk_khz = max_pclk_khz;

}



void hdmi_edid_deinit(void *input)

{

	struct hdmi_edid_ctrl *edid_ctrl = (struct hdmi_edid_ctrl *)input;

drivers/video/fbdev/msm/mdss_hdmi_edid.h

+1 −0
Original line number Diff line number Diff line
@@ -79,5 +79,6 @@ void hdmi_edid_get_hdr_data(void *edid_ctrl, 
		struct hdmi_edid_hdr_data **hdr_data);

void hdmi_edid_config_override(void *input, bool enable,

		struct hdmi_edid_override_data *data);

void hdmi_edid_set_max_pclk_rate(void *input, u32 max_pclk_khz);



#endif /* __HDMI_EDID_H__ */