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Commit eeb34111 authored by Oleg Perelet's avatar Oleg Perelet
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msm: kgsl: preserve ISENSE registers across GPU power collapse 



After wakeup from power collapse restore ISENSE registers from
internal buffer.

CRs-Fixed: 1075694
Change-Id: I9cf2f94892bdeb83fab0068902419b1603520364
Signed-off-by: default avatarOleg Perelet <operelet@codeaurora.org>
parent cd316285

drivers/gpu/msm/a5xx_reg.h

+6 −0
Original line number Diff line number Diff line
@@ -891,6 +891,11 @@ 
#define A5XX_GDPM_INT_MASK			0xB811

#define A5XX_GPMU_BEC_ENABLE			0xB9A0



/* ISENSE registers */

#define A5XX_GPU_CS_DECIMAL_ALIGN		0xC16A

#define A5XX_GPU_CS_SENSOR_PARAM_CORE_1	0xC126

#define A5XX_GPU_CS_SENSOR_PARAM_CORE_2	0xC127

#define A5XX_GPU_CS_SW_OV_FUSE_EN		0xC168

#define A5XX_GPU_CS_SENSOR_GENERAL_STATUS	0xC41A

#define A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_0	0xC41D

#define A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_2	0xC41F
@@ -898,5 +903,6 @@ 
#define A5XX_GPU_CS_ENABLE_REG			0xC520

#define A5XX_GPU_CS_AMP_CALIBRATION_CONTROL1	0xC557

#define A5XX_GPU_CS_AMP_CALIBRATION_DONE	0xC565

#define A5XX_GPU_CS_ENDPOINT_CALIBRATION_DONE   0xC556

#endif /* _A5XX_REG_H */

drivers/gpu/msm/adreno_a5xx.c

+38 −0
Original line number Diff line number Diff line
@@ -429,6 +429,43 @@ static int _poll_gdsc_status(struct adreno_device *adreno_dev, 
	return 0;

}



static void a5xx_restore_isense_regs(struct adreno_device *adreno_dev)

{

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	unsigned int reg, i, ramp = GPMU_ISENSE_SAVE;

	static unsigned int isense_regs[6] = {0xFFFF}, isense_reg_addr[] = {

		A5XX_GPU_CS_DECIMAL_ALIGN,

		A5XX_GPU_CS_SENSOR_PARAM_CORE_1,

		A5XX_GPU_CS_SENSOR_PARAM_CORE_2,

		A5XX_GPU_CS_SW_OV_FUSE_EN,

		A5XX_GPU_CS_ENDPOINT_CALIBRATION_DONE,

		A5XX_GPMU_TEMP_SENSOR_CONFIG};



	if (!adreno_is_a540(adreno_dev))

		return;



	/* read signature */

	kgsl_regread(device, ramp++, &reg);



	if (reg == 0xBABEFACE) {

		/* store memory locations in buffer */

		for (i = 0; i < ARRAY_SIZE(isense_regs); i++)

			kgsl_regread(device, ramp + i, isense_regs + i);



		/* clear signature */

		kgsl_regwrite(device, GPMU_ISENSE_SAVE, 0x0);

	}



	/* if we never stored memory locations - do nothing */

	if (isense_regs[0] == 0xFFFF)

		return;



	/* restore registers from memory */

	for (i = 0; i < ARRAY_SIZE(isense_reg_addr); i++)

		kgsl_regwrite(device, isense_reg_addr[i], isense_regs[i]);



}



/*

 * a5xx_regulator_enable() - Enable any necessary HW regulators

 * @adreno_dev: The adreno device pointer
@@ -478,6 +515,7 @@ static int a5xx_regulator_enable(struct adreno_device *adreno_dev) 
	kgsl_regrmw(device, A5XX_GPMU_GPMU_SP_CLOCK_CONTROL,

		CNTL_IP_CLK_ENABLE, 1);



	a5xx_restore_isense_regs(adreno_dev);

	return 0;

}

drivers/gpu/msm/adreno_a5xx.h

+1 −0
Original line number Diff line number Diff line
@@ -228,6 +228,7 @@ void a5xx_hwcg_set(struct adreno_device *adreno_dev, bool on); 
#define LM_SEQUENCE_ID			1

#define MAX_SEQUENCE_ID			3



#define GPMU_ISENSE_SAVE	(A5XX_GPMU_DATA_RAM_BASE + 200/4)

/* LM defaults */

#define LM_DEFAULT_LIMIT		6000

#define A530_DEFAULT_LEAKAGE		0x004E001A