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Commit ee79d2fe authored by Abhinav Kumar's avatar Abhinav Kumar
Browse files

drm/msm: reset TMDS clock ratio bit when disabling scrambler 



Currently, when scrambler is disabled the TMDS clock ratio bit
is left untouched. Ideally the sink should reset this bit during
hot plug OR no-signal cases. However, the HDMI spec requires this
bit to be explicitly reset by the source.

Add support to reset this bit during scrambler disable.

Change-Id: I092f6cae84653940e2bdb9100df5e384084cf938
Signed-off-by: default avatarAbhinav Kumar <abhinavk@codeaurora.org>
parent 58274ed8

drivers/gpu/drm/msm/hdmi-staging/sde_hdmi_bridge.c

+9 −0
Original line number Diff line number Diff line
@@ -351,6 +351,7 @@ static int _sde_hdmi_bridge_setup_scrambler(struct hdmi *hdmi, 
		scrambler_on = true;

		tmds_clock_ratio = 1;

	} else {

		tmds_clock_ratio = 0;

		scrambler_on = connector->supports_scramble;

	}
@@ -396,6 +397,14 @@ static int _sde_hdmi_bridge_setup_scrambler(struct hdmi *hdmi, 
		rc = _sde_hdmi_bridge_setup_ddc_timers(hdmi,

			HDMI_TX_DDC_TIMER_SCRAMBLER_STATUS, timeout_hsync);

	} else {

		/* reset tmds clock ratio */

		rc = sde_hdmi_scdc_write(hdmi,

				HDMI_TX_SCDC_TMDS_BIT_CLOCK_RATIO_UPDATE,

				tmds_clock_ratio);

		/* scdc write can fail if sink doesn't support SCDC */

		if (rc && connector->scdc_present)

			SDE_ERROR("SCDC present, TMDS clk ratio err\n");



		sde_hdmi_scdc_write(hdmi, HDMI_TX_SCDC_SCRAMBLING_ENABLE, 0x0);

		reg_val = hdmi_read(hdmi, REG_HDMI_CTRL);

		reg_val &= ~BIT(28); /* Unset SCRAMBLER_EN bit */