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Commit ea2d8a42 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
Browse files

drm/i915: Store the converted link rates in intel_dp->supported_rates[] 



No point in converting from hardware format every single time, just
store the rates in the final format under intel_dp.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarSonika Jindal <sonika.jindal@intel.com>
Reviewed-by: default avatarTodd Previte <tprevite@gmail.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent f4896f15

drivers/gpu/drm/i915/intel_dp.c

+19 −14
Original line number Original line Diff line number Diff line
@@ -1144,8 +1144,6 @@ static int 
intel_read_sink_rates(struct intel_dp *intel_dp, int *sink_rates)

intel_read_sink_rates(struct intel_dp *intel_dp, int *sink_rates)

{

{

	struct drm_device *dev = intel_dp_to_dev(intel_dp);

	struct drm_device *dev = intel_dp_to_dev(intel_dp);

	int i = 0;

	uint16_t val;





	if (INTEL_INFO(dev)->gen >= 9 && intel_dp->supported_rates[0]) {

	if (INTEL_INFO(dev)->gen >= 9 && intel_dp->supported_rates[0]) {

		/*

		/*
@@ -1153,18 +1151,12 @@ intel_read_sink_rates(struct intel_dp *intel_dp, int *sink_rates) 
		 * link rate table method, so read link rates from

		 * link rate table method, so read link rates from

		 * supported_link_rates

		 * supported_link_rates

		 */

		 */

		for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i) {

		memcpy(sink_rates, intel_dp->supported_rates,

			val = le16_to_cpu(intel_dp->supported_rates[i]);

		       sizeof(intel_dp->supported_rates));

			if (val == 0)

				break;



			sink_rates[i] = val * 200;

		}





		if (i <= 0)

		return intel_dp->num_supported_rates;

			DRM_ERROR("No rates in SUPPORTED_LINK_RATES");

	}

	}

	return i;

	return 0;

}

}





static int

static int
@@ -3754,10 +3746,23 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp) 
	    (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] &	DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&

	    (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] &	DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&

	    (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) &&

	    (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) &&

	    (rev >= 0x03)) { /* eDp v1.4 or higher */

	    (rev >= 0x03)) { /* eDp v1.4 or higher */

		__le16 supported_rates[DP_MAX_SUPPORTED_RATES];

		int i;



		intel_dp_dpcd_read_wake(&intel_dp->aux,

		intel_dp_dpcd_read_wake(&intel_dp->aux,

				DP_SUPPORTED_LINK_RATES,

				DP_SUPPORTED_LINK_RATES,

				intel_dp->supported_rates,

				supported_rates,

				sizeof(intel_dp->supported_rates));

				sizeof(supported_rates));



		for (i = 0; i < ARRAY_SIZE(supported_rates); i++) {

			int val = le16_to_cpu(supported_rates[i]);



			if (val == 0)

				break;



			intel_dp->supported_rates[i] = val * 200;

		}

		intel_dp->num_supported_rates = i;

	}

	}

	if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &

	if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &

	      DP_DWN_STRM_PORT_PRESENT))

	      DP_DWN_STRM_PORT_PRESENT))

drivers/gpu/drm/i915/intel_drv.h

+2 −1
Original line number Original line Diff line number Diff line
@@ -627,7 +627,8 @@ struct intel_dp { 
	uint8_t dpcd[DP_RECEIVER_CAP_SIZE];

	uint8_t dpcd[DP_RECEIVER_CAP_SIZE];

	uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];

	uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];

	uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];

	uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];

	__le16 supported_rates[DP_MAX_SUPPORTED_RATES];

	uint8_t num_supported_rates;

	int supported_rates[DP_MAX_SUPPORTED_RATES];

	struct drm_dp_aux aux;

	struct drm_dp_aux aux;

	uint8_t train_set[4];

	uint8_t train_set[4];

	int panel_power_up_delay;

	int panel_power_up_delay;